M34551 View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

M34551

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER

Renesas Electronics 

MITSUBISHI MICROCOMPUTERS

4551 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for

INFRARED REMOTE CONTROL TRANSMITTER

(1) External 0 interrupt request flag (EXF0)

External 0 interrupt request flag (EXF0) is set to “1” when a

valid waveform is input to D5/INT pin.

The valid waveforms causing the interrupt must be retained

at their level for 4 cycles or more of the system clock (Refer

to Figure 16).

The state of EXF0 flag can be examined with the skip

instruction (SNZ0). Use the interrupt control register V1 to

select the interrupt or the skip instruction. The EXF0 flag is

cleared to “0” when an interrupt occurs or when the next

instruction is skipped with the skip instruction.

The D5/INT pin need not be selected the external interrupt

input INT function or the normal output port D5 function.

However, the EXF0 flag is set to “1” when a valid waveform

output from port D5 is input to INT pin even if it is used as an

output port D5.

q External 0 interrupt activated condition

External 0 interrupt activated condition is satisfied when a

valid waveform is input to D5/INT pin.

The valid waveform can be selected from rising waveform or

falling waveform. An example of how to use the external 0

interrupt is as follows.

ΠSelect the valid waveform with the bit 2 of register I1.

 Clear the EXF0 flag to “0” with the SNZ0 instruction.

Ž Set the NOP instruction for the case when a skip is performed

with the SNZ0 instruction.

 Set both the external 0 interrupt enable bit (V10) and the

INTE flag to “1.”

The external 0 interrupt is now enabled. Now when a valid

waveform is input to the D5/INT pin, the EXF0 flag is set to

“1” and the external 0 interrupt occurs.

(2) External interrupt control register

q Interrupt control register I1

Register I1 controls the valid waveform for the external 0

interrupt. Set the contents of this register through register A

with the TI1A instruction. The TAI1 instruction can be used

to transfer the contents of register I1 to register A.

Table 8 External interrupt control register

Interrupt control register I1

at reset : 00002

at power down : state retained

R/W

I13 Not used

0

This bit has no function, but read/write is enabled.

1

0 Falling waveform (“L” level of INT pin is recognized with the SNZI0

Interrupt valid waveform for INT pin

instruction)

I12

selection bit (Note 2)

1 Rising waveform (“H” level of INT pin is recognized with the SNZI0

instruction)

I11 Not used

0

This bit has no function, but read/write is enabled.

1

I10 Not used

0

This bit has no function, but read/write is enabled.

1

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: Depending on the input state of D5/INT pin, the external interrupt request flag EXF0 may be set to “1” when the contents of

I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after

executing at least one instruction.

17

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