M34551 View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

M34551

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER

Renesas Electronics 

MITSUBISHI MICROCOMPUTERS

4551 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for

INFRARED REMOTE CONTROL TRANSMITTER

WATCHDOG TIMER

Watchdog timer provides a method to reset the system when a

program runs wild. Watchdog timer consists of timer 2, watchdog

timer enable flag (WEF), and watchdog timer flag (WDF).

When the WRST instruction is executed after system is released

from reset, the WEF flag is set to “1.” At this time, the watchdog

timer starts operating. When the WEF flag is set to “1,” it cannot

be cleared to “0” until system reset is performed. Also, when the

WRST instruction is not executed once, watchdog timer does

not operate because the WEF flag retains “0.”

When the watchdog timer is operating, the WDF flag is set to “1”

every time the bit 12 of timer 2 is cleared from “1” to “0.” This

means that count is performed 8192 times. When the bit 12 of

timer 2 is cleared from “1” to “0” while the WDF flag is set to “1,”

the internal reset signal is generated and system reset is

performed.

The WDF flag can be cleared to “0” with the WRST instruction.

In the RAM back-up mode, through timer 2 count operation stops,

its count value is retained and the WDF flag is initialized.

In the clock operating mode, timer 2 count operation is continued

and the WDF flag is initialized.

When using the watchdog timer, execute the WRST instruction

at a certain cycle which consists of timer 2’s 8191 counts or less

to keep the microcomputer operation normal.

3FFF16

Value of timer 2 1FFF16

0000 16

WEF flag

“1”

“0”

WDF flag “1”

“0”

Internal reset

signal

“H”

“L”

WRST instruction WRST instruction

execution

execution

System reset

Fig. 20 Watchdog timer function

The contents of the WDF flag are initialized in the RAM back-up

mode.

If the WDF flag is set to “1” at the same time that the

microcomputer enters the RAM back-up mode, system reset may

be performed.

When using the watchdog timer and the RAM back-up mode,

initialize the WDF flag with the WRST instruction just before the

microcomputer enters the RAM back-up mode (refer to Figure

21).

•••

•••

WRST

EPOF

POF2

; Clear WDF flag

; POF instruction execution enabled

Oscillation stop (RAM back-up mode)

Fig. 21 Program example to enter the RAM back-up mode

when using the watchdog timer

22

Share Link: