IS61LV256 View Datasheet(PDF) - Integrated Silicon Solution

Part Name

Description

Manufacturer

IS61LV256

32K x 8 LOW VOLTAGE CMOS STATIC RAM

Integrated Silicon Solution 

IS61LV256

ISSI®

READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)

Symbol Parameter

tRC Read Cycle Time

tAA Address Access Time

tOHA

tACE

tDOE

tLZOE(2)

tHZOE(2)

tLZCE(2)

tHZCE(2)

tPU(3)

tPD(3)

Output Hold Time

CE Access Time

OE Access Time

OE to Low-Z Output

OE to High-Z Output

CE to Low-Z Output

CE to High-Z Output

CE to Power-Up

CE to Power-Down

-12 ns

Min. Max.

12 —

— 12

2—

— 12

—6

0—

—7

3—

—5

0—

— 13

-15 ns

Min. Max.

15 —

— 15

2—

— 15

—7

0—

—8

3—

—6

0—

— 15

-20 ns

Min. Max.

20 —

— 20

2—

— 20

—8

0—

—9

3—

—9

0—

— 18

-25 ns

Min. Max. Unit

25 —

ns

— 25

ns

2—

ns

— 25

ns

—9

ns

0—

ns

— 10

ns

3—

ns

— 10

ns

0—

ns

— 20

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. Not 100% tested.

AC TEST CONDITIONS

Parameter

Input Pulse Level

Input Rise and Fall Times

Input and Output Timing

and Reference Levels

Output Load

Unit

0V to 3.0V

3 ns

1.5V

See Figures 1a and 1b

AC TEST LOADS

3.3V

635 Ω

OUTPUT

30 pF

Including

jig and

scope

702 Ω

Figure 1a.

3.3V

635 Ω

OUTPUT

5 pF

Including

jig and

scope

702 Ω

Figure 1b.

2-4

Integrated Silicon Solution, Inc.

Rev. F 0296

SR81995LV61

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