IS61LV256 View Datasheet(PDF) - Integrated Silicon Solution

Part Name

Description

Manufacturer

IS61LV256

32K x 8 LOW VOLTAGE CMOS STATIC RAM

Integrated Silicon Solution 

IS61LV256

ISSI®

WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)

Symbol Parameter

tWC Write Cycle Time

tSCE CE to Write End

tAW Address Setup Time to Write End

tHA Address Hold from Write End

tSA Address Setup Time

WE tPWE(4)

Pulse Width

tSD Data Setup to Write End

tHD

tHZWE(2)

tLZWE(2)

Data Hold from Write End

WE LOW to High-Z Output

WE HIGH to Low-Z Output

-12 ns

Min. Max.

12 —

8—

8—

0—

0—

8—

6—

0—

—6

0—

-15 ns

Min. Max.

15 —

10 —

10 —

0—

0—

10 —

8—

0—

—7

0—

-20 ns

Min. Max.

20 —

13 —

15 —

0—

0—

13 —

10 —

0—

—8

0—

-25 ns

Min. Max. Unit

25 —

ns

15 —

ns

20 —

ns

0—

ns

0—

ns

15 —

ns

12 —

ns

0—

ns

— 10

ns

0—

ns

Notes:

1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

4. Tested with OE HIGH.

AC WAVEFORMS

WRITE CYCLE NO. 1 (WE Controlled)(1,2)

ADDRESS

CE

WE

DOUT

DIN

tWC

tSCE

tHA

tAW

tPWE

tSA

tHZWE

DATA UNDEFINED

HIGH-Z

tLZWE

tSD

tHD

DATA-IN VALID

2-6

Integrated Silicon Solution, Inc.

Rev. F 0296

SR81995LV61

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