EP1C3T256I7N View Datasheet(PDF) - Altera Corporation

Part Name

Description

Manufacturer

EP1C3T256I7N

Cyclone FPGA Family Data Sheet

Altera Corporation 

Cyclone Device Handbook, Volume 1

preset/load, synchronous clear, synchronous load, and clock enable

control for the register. These LAB-wide signals are available in all LE

modes. The addnsub control signal is allowed in arithmetic mode.

The Quartus II software, in conjunction with parameterized functions

such as library of parameterized modules (LPM) functions, automatically

chooses the appropriate mode for common functions such as counters,

adders, subtractors, and arithmetic functions. If required, you can also

create special-purpose functions that specify which LE operating mode to

use for optimal performance.

Normal Mode

The normal mode is suitable for general logic applications and

combinatorial functions. In normal mode, four data inputs from the LAB

local interconnect are inputs to a four-input LUT (see Figure 2–6). The

Quartus II Compiler automatically selects the carry-in or the data3

signal as one of the inputs to the LUT. Each LE can use LUT chain

connections to drive its combinatorial output directly to the next LE in the

LAB. Asynchronous load data for the register comes from the data3

input of the LE. LEs in normal mode support packed registers.

Figure 2–6. LE in Normal Mode

sload

sclear

(LAB Wide) (LAB Wide)

Register chain

connection

aload

(LAB Wide)

addnsub (LAB Wide)

(1)

data1

data2

data3

cin (from cout

of previous LE)

data4

4-Input

LUT

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

ALD/PRE

ADATA Q

D

ENA

CLRN

Row, column, and

direct link routing

Row, column, and

direct link routing

Local routing

LUT chain

connection

Register Feedback

Note to Figure 2–6:

(1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.

Register

chain output

2–8

Preliminary

Altera Corporation

May 2008

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