74HCT123-Q100 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
74HCT123-Q100 Datasheet PDF : 23 Pages
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NXP Semiconductors
74HC123-Q100; 74HCT123-Q100
Dual retriggerable monostable multivibrator with reset
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
trtrig
retrigger
nA, nB; CEXT = 0 pF; REXT = [3][4] - 110 -
-
-
-
- ns
time
5 k; VCC = 5.0 V;
see Figure 10
REXT
external
timing
resistor
VCC = 5.0 V; see Figure 7
2 - 1000 -
-
-
- k
CEXT external
VCC = 5.0 V; see Figure 7
[4] -
-
-
-
-
-
- pF
timing
capacitor
CPD
power
per monostable; VI = GND
[5] -
56
-
-
-
-
- pF
dissipation to VCC
capacitance
[1] tpd is the same as tPHL and tPLH; tt is the same as tTHL and tTLH
[2] For other REXT and CEXT combinations, see Figure 7. If CEXT > 10 nF, the following formula is valid.
tW = K REXT CEXT, where:
tW = typical output pulse width in ns;
REXT = external resistor in k;
CEXT = external capacitor in pF;
K = constant = 0.45 for VCC = 5.0 V and 0.55 for VCC = 2.0 V.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is approximately 7 pF.
[3] The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT. The output pulse width is only extended
when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time. If CEXT >10 pF, the next
formula (at VCC = 5.0 V) for the setup time of a retrigger pulse is valid:
trtrig = 30 + 0.19 REXT CEXT0.9 + 13 REXT1.05, where:
trtrig = retrigger time in ns;
CEXT = external capacitor in pF; REXT = external resistor in k.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is 7 pF.
[4] When the device is powered-up, initiate the device via a reset pulse, when CEXT < 50 pF.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) + 0.75 CEXT VCC2 fo + D 16 VCC where:
fi = input frequency in MHz;
fo = output frequency in MHz;
D = duty factor in %;
CL = output load capacitance in pF;
VCC = supply voltage in V;
CEXT = timing capacitance in pF;
(CL VCC2 fo) sum of outputs.
74HC_HCT123_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 1 August 2012
© NXP B.V. 2012. All rights reserved.
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