LC8901Q View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
Manufacturer
LC8901Q Datasheet PDF : 15 Pages
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LC8901, 8901Q
Microprocessor Interface Output
The table lists the content of the bits D0 to D15 in the microprocessor interface format.
Bit
D0
D1
D2
D3
D4
D5 to D12
D13 D15
Meaning
Invalid bit. A low level is always output.
Indicate the sampling frequency.
Correspond to the 2 external output port pins.
Indicates the copy flag.
Low: copy protected, high: copying allowed.
Outputs the first bit in the channel status bits.
These bits serially output the 8 bits of the channel status category code.
Invalid bit. A low level is always output.
Interpretation of Bits D1 and D2
Sampling frequency
32 kHz 44.1 kHz 48 kHz
#1
D1
H
L
L
H
D2
H
L
H
L
1. The #1 state is the state in which the data was cleared by a PLL lock error.
2. The initial settings of the modes immediately after the XMODE pin is switched from low to high are all low level.
However, D1 and D2 will indicate the #1 state.
3. The microprocessor data output registers are all cleared to 0 when PLL locking is lost. However, D1 and D2 will
indicate the #1 state.
4. The interval between two microprocessor data readout operations must be at least 6 ms. Also, when PLL locking is
lost the microprocessor must wait at least 6 ms after the error signal goes low before accessing data.
FS Code
The SUB1 and SUB2 pins indicate the input data sampling frequency.
Sampling frequency
32 kHz 44.1 kHz 48 kHz
#1
SUB1
H
L
L
H
SUB2
H
L
H
L
The #1 state is the state in which the data was cleared by a PLL lock error.
Lock and Errors
1. LOCK pin: This pin goes high when preamble detection has succeeded for 2 consecutive frames and thus indicates
the PLL locked state. This pin is low at all other times. In particular, it is low when the XMODE pin is low, when the
STOP pin is high, and in analog source mode.
2. ERROR pin: Goes high when an error exists in the input data or when the PLL circuit is in the unlocked state. When
the data returns to normal it holds the high level for about 200 to 300 ms and then falls to low. This period is
inversely proportional to the input data sampling frequency. This pin is high when the XMODE pin is low, when the
STOP pin is high, and in analog source mode.
3. Data processing when errors occur: The table below lists the data processing that is performed when an error occurs.
Error type
Continuous parity errors for up to 8 cycles
Continuous parity errors for 9 or more cycles
PLL lock error
Audio output data
The previous data value is output
All zero data is output
All zero data is output
C bit output data
Held
Held
Data is cleared and the #1 state is indicated.
Note: The term “C bit data” means data that was decoded from the channel status bit.
• When there is no data input to the data demodulation system, the system automatically switches from PLL
operation to the crystal oscillator and enters analog source mode.
• These pins indicate a state identical to a PLL lock error in any of the following cases: The STOP pin is high, the
XMODE pin is low, or the system is in analog source mode.
No. 4079-11/15
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