AD7660(2016) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7660 Datasheet PDF : 20 Pages
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AD7660
Parameter
Conditions
Min
Typ
Max
TEMPERATURE RANGE
Specified Performance
TMIN to TMAX
–40
+85
NOTES
1LSB means least significant bit. With the 0 V to 2.5 V input range, one LSB is 38.15 mV.
2Typical rms noise at worst-case transitions and temperatures.
3See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
4All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
5Tested in Parallel Reading Mode.
6With all digital inputs forced to DVDD or DGND respectively.
Specifications subject to change without notice.
Unit
∞C
TIMING SPECIFICATIONS (–40؇C to +85؇C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
REFER TO FIGURES 11 AND 12
Convert Pulsewidth
Time between Conversions
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read after Convert Mode
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
t1
5
t2
10
t3
t4
ns
ms
15
ns
2
ms
t5
2
ns
t6
10
ns
t7
2
ms
t8
8
ms
t9
10
ns
REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t10
DATA Valid to BUSY LOW Delay
t11
45
Bus Access Request to DATA Valid
t12
Bus Relinquish Time
t13
5
2
ms
ns
40
ns
15
ns
REFER TO FIGURE 16 AND 17 (Master Serial Interface Modes)1
CS LOW to SYNC Valid Delay
t14
CS LOW to Internal SCLK Valid Delay
t15
CS LOW to SDOUT Delay
t16
CNVST LOW to SYNC Delay
t17
SYNC Asserted to SCLK First Edge Delay
t18
Internal SCLK Period
t19
Internal SCLK HIGH (INVSCLK Low)2
t20
Internal SCLK LOW (INVSCLK Low)2
t21
SDOUT Valid Setup Time
t22
SDOUT Valid Hold Time
t23
SCLK Last Edge to SYNC Delay
t24
CS HIGH to SYNC HI-Z
t25
CS HIGH to Internal SCLK HI-Z
t26
CS HIGH to SDOUT HI-Z
t27
BUSY HIGH in Master Serial Read after Convert
t28
CNVST LOW to SYNC Asserted Delay
t29
SYNC Deasserted to BUSY LOW Delay
t30
10
ns
10
ns
10
ns
500
ns
4
ns
40
75
ns
30
ns
9.5
ns
4.5
ns
3
ns
3
10
ns
10
ns
10
ns
3.2
ms
1.5
ms
50
ns
REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)1
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
t31
5
t32
3
t33
5
t34
5
t35
25
t36
10
t37
10
ns
16
ns
ns
ns
ns
ns
ns
NOTES
1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum.
2If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.
REV. E
–3–
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