AT89S51(2001) View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
| AT89S51 Datasheet PDF : 0 Pages | |||
AT89S51
WDT During
Power-down
and Idle
UART
Timer 0 and 1
Interrupts
should be serviced in those sections of code that will periodically be executed within the time
required to prevent a WDT reset.
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
down mode, the user does not need to service the WDT. There are two methods of exiting
Power-down mode: by a hardware reset or via a level-activated external interrupt, which is
enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,
servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To pre-
vent the WDT from resetting the device while the interrupt pin is held low, the WDT is not
started until the interrupt is pulled high. It is suggested that the WDT be reset during the inter-
rupt service for the interrupt used to exit Power-down mode.
To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best
to reset the WDT just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether
the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit =
0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode,
the user should always set up a timer that will periodically exit IDLE, service the WDT, and
reenter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count
upon exit from IDLE.
The UART in the AT89S51 operates the same way as the UART in the AT89C51. For further
information on the UART operation, refer to the ATMEL Web site (http://www.atmel.com).
From the home page, select ‘Products’, then ‘8051-Architecture Flash Microcontroller’, then
‘Product Overview’.
Timer 0 and Timer 1 in the AT89S51 operate the same way as Timer 0 and Timer 1 in the
AT89C51. For further information on the timers’ operation, refer to the ATMEL Web site
(http://www.atmel.com). From the home page, select ‘Products’, then ‘8051-Architecture Flash
Microcontroller’, then ‘Product Overview’.
The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two
timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in
Figure 1.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a
bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.
Note that Table 4 shows that bit position IE.6 is unimplemented. In the AT89S51, bit position
IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they
may be used in future AT89 products.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers
overflow. The values are then polled by the circuitry in the next cycle
9
2487A–10/01
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