MPC9893AE View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
MPC9893AE Datasheet PDF : 14 Pages
| |||
MPC9893 Data Sheet
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
Table 8. AC Characteristics (VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, TA = –40° to 85°C)(1)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
FSEL=000x
15.0
FSEL=001x
30.0
FSEL=010x
40.0
FSEL=011x
30.0
FSEL=100x
60.0
FSEL=101x
15.0
FSEL=110x
30.0
FSEL=111x
60.0
25.0
50.0
66.6
50.0
100.0
12.5
50.0
100.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
fMAX Maximum Output Frequency
FSEL=000x
60.0
FSEL=001x
60.0
FSEL=010x
60.0
FSEL=011x
30.0
FSEL=100x
60.0
FSEL=101x
7.5
FSEL=110x
15.0
FSEL=111x
30.0
200.0
200.0
200.0
100.0
200.0
25.0
50.0
100.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
frefDC
tr, tf
t()
t
tsk(O)
Reference Input Duty Cycle
CLK0, 1 Input Rise/Fall Time
Propagation Delay (static phase offset, CLKx to FB)
VCC=3.3 V5% and FSEL[0:2]=111
VCC=3.3 V5%
VCC=2.5 V5% and FSEL[0:2]=111
VCC=2.5 V5%
Rate of Period Change (phase slew rate)
QAx outputs
QBx outputs (FSEL=xxx0)
QBx outputs (FSEL=xxx1)
Output-to-Output Skew(2)
(within bank)
(bank-to-bank)
(any output to QFB)
40
–60
–200
–125
–400
60
1.0
+50
+100
+25
+100
150
150
300
150
100
125
%
ns 0.8 to 2.0 V
PLL locked
ps
ps
ps
ps
Failover switch
ps/cycle
ps
ps
ps
DCO Output Duty Cycle
45
tr, tf Output Rise/Fall Time
0.1
tPLZ, HZ Output Disable Time
tPZL, LZ
tJIT(CC)
Output Enable Time
Cycle-to-Cycle Jitter(3)
FSEL3=0
FSEL3=1
tJIT(PER) Period Jitter(3)
FSEL3=0
FSEL3=1
tJIT()
I/O Phase Jitter(4)
FB=4: FSEL[0:2]=100 or 111
FB=6: FSEL[0:2]=010
FB=8: FSEL[0:2]=001, 011, or 110
FB=16: FSEL[0:2]=000 or 101
RMS (1 )
RMS (1 )
RMS (1 )
RMS (1 )
BW
PLL Closed Loop Bandwidth(5)
FSEL=111x
50
0.8-4.0
55
%
1.0
ns 0.55 to 2.4 V
10
ns
10
ns
225
ps See applications
425
ps section
150
ps See applications
250
ps section
See applications
40
ps section
50
ps
55
ps
70
ps
MHz
tLOCK Maximum PLL Lock Time
10
ms
1. AC characteristics apply for parallel output termination of 50 to VTT.
2. See application section for part-to-part skew calculation.
3. Cycle-to-cycle and period jitter depend on the VCO frequency and output configuration. See the application section.
4. I/O jitter depends on the VCO frequency and internal PLL feedback divider FB. See APPLICATIONS INFORMATION for more information
and for the calculation for other confidence factors than 1
5. –3dB point of PLL transfer characteristics.
MPC9893 REVISION 8 3/16/16
6
©2016 Integrated Device Technology, Inc.
Share Link: 