MPC9893AE View Datasheet(PDF) - Integrated Device Technology
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MPC9893AE Datasheet PDF : 14 Pages
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MPC9893 Data Sheet
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
RF = 5–15 CF = 22F
RF
VCC
VCC_PLL
CF
10 nF
MPC9893
VCC
33...100 nF
Figure 3. VCC_PLL Power Supply Filter
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 3, the filter cut-off frequency is around
3-5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9893 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Using the MPC9893 in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC9893. Designs using the MPC9893 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9893 clock driver allows for its use as a zero delay
buffer. The the propagation delay through the device is
virtually eliminated. The PLL aligns the feedback clock output
edge with the clock input reference edge resulting a near zero
delay through the device. The maximum insertion delay of the
device in zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or long-
term jitter), feedback path delay and the output-to-output
skew error relative to the feedback output.
Calculation of Part-to-Part Skew
The MPC9893 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9893 are connected together, the maximum overall
timing uncertainty from the common CLK0 or CLK1 input to
any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of four
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
TCLKCommon
—t(ý)
tPD,LINE(FB)
QFBDevice 1
Any QDevice 1
tJIT()
+tSK(O)
QFBDevice2
+t()
tJIT()
Any QDevice 2
Max. skew
+tSK(O)
tSK(PP)
Figure 4. MPC9893 Max. Device-to-Device Skew
Due to the statistical nature of I/O jitter a RMS value (1 )
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 9.
Table 9. Confidence Factor CF
CF
1
2
3
4
5
6
Probability of clock edge within the distribution
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a I/
O jitter confidence factor of 99.7% ( 3) is assumed,
resulting in a worst case timing uncertainty from the common
clock input to any MPC9893 output of –275 ps to +265 ps
relative to the reference clock input CLK0/1:
tSK(PP) = [–60ps...50ps] + [-125ps...125ps] +
[(30ps –3)...(30ps 3)] + tPD, LINE(FB)
tSK(PP) = [–275ps...265ps] + tPD, LINE(FB)
Example configuration: fref = 100 MHz, VCC = 3.3 V
fVCO = 400 MHz, FSEL[0:2]=111
MPC9893 REVISION 8 3/16/16
8
©2016 Integrated Device Technology, Inc.
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