MPC9893AE View Datasheet(PDF) - Integrated Device Technology
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MPC9893AE Datasheet PDF : 14 Pages
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MPC9893 Data Sheet
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
The I/O (Phase) jitter of the MPC9893 depends on the
internal VCO frequency and the PLL feedback divider
configuration. A high internal VCO frequency and a low PLL
feedback divider result in lower I/O jitter than the jitter limits in
the AC characteristics (Table 8). When calculating the part-
to-part skew, Table 10 should be used to determine the actual
VCO frequency, then use Figure 5 to determine the maximum
I/O jitter for the specific VCO frequency and divider
configuration. In above example calculation, the internal VCO
frequency of 400 MHz corresponds to a maximum I/O jitter of
30 ps (RMS).
Table 10. Internal VCO Frequency fVCO
MPC9893
Configuration
fVCO
PLL Feedback
Divider FB
M1H, M12H, M2H, M22H
4 * fref
4
M3, M32
6 * fref
6
M1M, M12M, M2M, M22M,
8 * fref
8
M4, M42
M1L, M12L, M8, M82
16 * fref
16
I/O Phase Jitter versus Frequency
Parameter: PLL/Feedback Configuration
FB=16: FSEL[0:2]=000, 101
70
60
FB=8: FSEL[0:2]=001, 011, 110
50
40
30
20
FB=6: FSEL[0:2}=010
10
FB=4: FSEL[0:2]=100, 111
0
240
260
280
300
320
340
360
380
400
VCO frequency [MHz]
Figure 5. Max. I/O Phase Jitter versus VCO Frequency
The cycle-to-cycle jitter and period jitter of the MPC9893
depend on the output configuration and on the frequency of
the internal VCO. Using the outputs of bank A and bank B at
the same frequency (FSEL3=0) results in a lower jitter than
the split output frequency configuration (FSEL3=1). The jitter
also decreases with an increasing internal VCO frequency.
Figure 5 to Figure 7 represent the maximum jitter of the
MPC9893.
Cycle-to-Cycle Jitter versus Frequency
Parameter: Output Configuration
500
400
PSEL3=1
300
200
PSEL3=0
100
VCO Frequency
Period Jitter versus Frequency
Parameter: Output Configuration
300
250
PSEL=xxx1
200
150
PSEL=xxx0
100
50
0
240 260 280 300 320 340 360 380 400
VCO frequency [MHz]
Figure 7. Max. Period Jitter versus VCO Frequency
Driving Transmission Lines
The MPC9893 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale Semiconductor
application note AN1091. In most high performance clock
networks point-to-point distribution of signals is the method of
choice. In a point-to-point scheme either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50 resistance to VCC2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9893 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 8 illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme
the fanout of the MPC9893 clock driver is effectively doubled
due to its capability to drive multiple lines.
MPC9893
Output
Buffer
In
14
RS = 36
ZO = 50
OutA
MPC9893
Output
Buffer
RS = 36
ZO = 50
OutB0
In
14
RS = 36
ZO = 50
OutB1
0
240 260 280 300 320 340 360 380 400
VCO frequency [MHz]
Figure 6. Max. Cycle-to-Cycle Jitter versus
Figure 8. Single versus Dual Transmission Lines
MPC9893 REVISION 8 3/16/16
9
©2016 Integrated Device Technology, Inc.
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