Package pinout and device pin description
ST7LUS5, ST7LU05, ST7LU09
2
Package pinout and device pin description
Figure 2. 8-pin SO package pinout
VDD 1
8 VSS
PA5 (HS)/AIN4/CLKIN 2) ei4 ei0 (7 PA0 (HS)/AIN0/ATPWM/ICCDATA
PA4 (HS)/AIN3/MCO 3) ei3 ei1 (6 PA1 (HS)/AIN1/ICCCLK
PA3/RESET 4
ei2 (5 PA2 (HS)/LTIC/AIN2
OObbssoolleettee PPrroodduucctt((ss)) -- OObbssoolleettee PPrroodduucctt((ss)) Note:
(HS): High sink capability
eix: associated external interrupt vector
Figure 3. 16-pin DIP package pinout(a)
Reserved(1) 1
16 NC
VDD 2
RESET 3
15 VSS
ei0 14 PA0 (HS)/AIN0/ATPWM
ICCCLK 4
ei1 13 PA1 (HS)/AIN1
PA5 (HS)/AIN4/CLKIN 5 ei4
12 NC
PA4 (HS)/AIN3/MCO 6 ei3
11 ICCDATA
PA3 7
NC 8
ei2 10 PA2 (HS)/LTIC/AIN2
9 NC
(HS): High sink capability
eix: associated external interrupt vector
1. Must be tied to ground
The differences between 16-pin and 8-pin packages are listed below:
1. The ICC signals (ICCCLK and ICCDATA) are mapped on dedicated pins.
2. The reset signal is mapped on a dedicated pin. It is not multiplexed with PA3.
3. PA3 pin is always configured as output. Any change on multiplexed IO reset control
registers (MUXCR1 and MUXCR2) will have no effect on PA3 functionality. Refer to
Section 4.6: Register description.
a. For development or tool prototyping purposes only. Package not orderable in production quantities.
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