BLOCK DIAGRAM
A2V64S40CTP
64M Single Data Rate Synchronous DRAM
www.DataSheet.co.kr
Note:This figure shows the A2V64S30CTP
The A2V64S20CTP configuration is 4096x1024x4 of cell array and DQ0-3
The A2V64S40CTP configuration is 4069x256x16 of cell array and DQ0-15
Type Designation Code
A2V64S40CTP-G5
Speed Grade 7: 143MHz@CL=3
6: 166MHz@CL=3
5: 200MHz@CL=3
Package Type TP:TSOP (II)
Process Generation
Function Reserved for Future Use
Organization 2n 3:x8, 4:x16
SDR Synchronous DRAM
Density 64:64M bits
Interface V:LVTTL
Memory Style (DRAM)
Zentel DRAM
Revision 2.1
Page 2/36
Sep., 2008
Datasheet pdf - http://www.DataSheet4U.net/