LH28F008SC-L120 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
Manufacturer
LH28F008SC-L120 Datasheet PDF : 55 Pages
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sharp
LHF08CH1
28
DC Characteristics (Continued)
Sym.
Parameter
VCC=2.7V VCC=3.3V
VCC=5V
Notes Min. Max. Min. Max. Min. Max. Unit
Test
Conditions
VIL Input Low Voltage
VIH Input High Voltage
7 -0.5 0.8 -0.5 0.8 -0.5 0.8 V
7
2.0
VCC
+0.5
2.0
VCC
+0.5
2.0
VCC
+0.5
V
VOL Output Low Voltage
VOH1 Output High Voltage
(TTL)
VOH2 Output High Voltage
(CMOS)
VPPLK VPP Lockout during
Normal Operations
3,7
0.4
0.4
0.45
3,7
2.4
2.4
2.4
3,7 0.85
0.85
0.85
VCC
VCC
VCC
VCC
VCC
VCC
-0.4
-0.4
-0.4
4,7
1.5
1.5
1.5
VCC=VCCMin.
V
IOL=5.8mA(VCC=5V)
IOL=2.0mA
(VCC=3.3V, 2.7V)
VCC=VCCMin.
V
IOH=-2.5mA(VCC=5V)
IOH=-2.0mA(VCC=3.3V)
IOH=-1.5mA(VCC=2.7V)
V
VCC=VCCMin.
IOH=-2.0mA
V
VCC=VCCMin.
IOH=-100µA
V
VPPH1 VPP during Byte Write,
Block Erase or
  3.0 3.6   V
Lock-Bit Operations
VPPH2 VPP during Byte Write,
Block Erase or
  4.5 5.5 4.5 5.5 V
Lock-Bit Operations
VPPH3 VPP during Byte Write,
Block Erase or
  11.4 12.6 11.4 12.6 V
Lock-Bit Operations
VLKO VCC Lockout Voltage
VHH RP# Unlock Voltage
2.0
8,9

2.0
2.0
V
Set master lock-bit
 11.4 12.6 11.4 12.6 V Override master and
block lock-bit
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA=+25°C.
2. ICCWS and ICCES are specified with the device de-selected. If read or byte written while in erase suspend mode,
the device’s current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively.
3. Includes RY/BY#.
4. Block erases, byte writes, and lock-bit configurations are inhibited when VPP≤VPPLK, and not guaranteed in the
range between VPPLK(max.) and VPPH1(min.), between VPPH1(max.) and VPPH2(min.), between VPPH2(max.)
and VPPH3(min.), and above VPPH3(max.).
5. Automatic Power Savings (APS) reduces typical ICCR to 1mA at 5V VCC and 3mA at 2.7V and 3.3V VCC in static
operation.
6. CMOS inputs are either VCC±0.2V or GND±0.2V. TTL inputs are either VIL or VIH.
7. Sampled, not 100% tested.
8. Master lock-bit set operations are inhibited when RP#=VIH. Block lock-bit configuration operations are inhibited
when the master lock-bit is set and RP#=VIH. Block erases and byte writes are inhibited when the corresponding
block-lock bit is set and RP#=VIH. Block erase, byte write, and lock-bit configuration operations are not
guaranteed with VCC<3.0V or VIH<RP#<VHH and should not be attempted.
9. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
Rev. 1.3
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