IS43TR16640A-125KBL View Datasheet(PDF) - Integrated Silicon Solution
Part Name
Description
Manufacturer
IS43TR16640A-125KBL Datasheet PDF : 71 Pages
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IS43TR16640A, IS43TR81280A
4.3. AC and DC Logic Input Levels for Differential Signals
4.3.1 Differential signal definition
Figure 4.3.1 Definition of differential ac-swing and “time above ac-level”
VIH.DIFF.AC.MIN
tDVAC
VIH.DIFF.MIN
Half cycle
VIH.DIFF.MAX
VIH.DIFF.AC.MAX
tDVAC
time
4.3.2 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#)
4.3.2.1 Differential AC and DC Input Levels
Symbol
Parameter
DDR3-800, 1066, 1333, & 1600
Min
Max
unit
Notes
VIHdiff
Differential input logic high
+0.200
Note3
V
1
VILdiff
Differential input logic low
Note3
-0.200
V
1
VIHdiff(ac)
Differential input high ac
2 x ( VIH(ac) – Vref )
Note3
V
2
VILdiff(ac)
Differential input low ac
Note3
2 x ( Vref - VIL(ac) )
V
2
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK# use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS#, DQSL, DQSL#, DQSU, DQSU# use VIH/VIL(ac) of DQs and VREFDQ; if
a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals CK, CK#, DQS, DQS#, DQSL, DQSL#, DQSU, DQSU# need to be within the
respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot.
4.3.2.2 Allowed time before ringback (tDVAC) for CK - CK# and DQS - DQS#
Slew Rate [V/ns]
tDVAC [ps] @IVIH/Ldiff(ac)I = 350mV
tDVAC [ps] @IVIH/Ldiff(ac)I = 300mV
min
max
min
max
> 4.0
75
-
175
-
4.0
57
-
170
-
3.0
50
-
167
-
2.0
38
-
163
-
1.8
34
-
162
-
1.6
29
-
161
-
1.4
22
-
159
-
1.2
13
-
155
-
1.0
0
-
150
-
< 1.0
0
-
150
-
Integrated Silicon Solution, Inc. – www.issi.com –
31
Rev. 00A
04/16/2012
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