Micrel, Inc.
KSZ9031RNX
Strapping Options
Pin Number
35
15
17
Pin Name
PHYAD2
PHYAD1
PHYAD0
27
MODE3
28
MODE2
31
MODE1
32
MODE0
33
CLK125_EN
41
LED_MODE
Note:
1. I/O = Bi-directional.
Type(1)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin Function
The PHY address, PHYAD[2:0], is sampled and latched at power-up/reset and is
configurable to any value from 0 to 7. Each PHY address bit is configured as follows:
Pull-up = 1
Pull-down = 0
PHY address bits [4:3] are always set to ‘00’.
The MODE[3:0] strap-in pins are sampled and latched at power-up/reset as follows:
MODE[3:0]
Mode
0000
Reserved – not used
0001
Reserved – not used
0010
Reserved – not used
0011
Reserved – not used
0100
NAND tree mode
0101
Reserved – not used
0110
Reserved – not used
0111
Chip power-down mode
1000
Reserved – not used
1001
Reserved – not used
1010
Reserved – not used
1011
Reserved – not used
1100
RGMII mode – advertise 1000Base-T full-duplex only
1101
RGMII mode – advertise 1000Base-T full- and half-duplex only
1110
RGMII mode – advertise all capabilities (10/100/1000 speed
half-/full-duplex), except 1000Base-T half-duplex
1111
RGMII mode – advertise all capabilities (10/100/1000 speed
half-/full-duplex)
CLK125_EN is sampled and latched at power-up/reset and is defined as follows:
Pull-up = Enable 125MHz clock output
Pull-down = Disable 125MHz clock output
Pin 41 (CLK125_NDO) provides the 125MHz reference clock output option for use by
the MAC.
LED_MODE is latched at power-up/reset and is defined as follows:
Pull-up = Single-LED mode
Pull-down = Tri-color dual-LED mode
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during
power-up or reset, and consequently cause the PHY strap-in pins on the RGMII signals to be latched to an incorrect
configuration. In this case, Micrel recommends adding external pull-ups/pull-downs on the PHY strap-in pins to ensure the
PHY is configured to the correct pin strap-in mode.
October 2012
15
M9999-103112-1.0