KSZ9031RNX View Datasheet(PDF) - Micrel

Part Name

Description

Manufacturer

KSZ9031RNX

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9031RNX

Table 19. RGMII v2.0 Specification (Timing Specifics from Table 2)

Timing Parameter Description

TskewT

Data to clock output skew (at transmitter) per RGMII v1.3 (external

delay)

TskewR

TsetupT

TholdT

TsetupR

Data to clock input skew (at receiver) per RGMII v1.3 (external delay)

Data to clock output setup (at transmitter – integrated delay)

Clock to data output hold (at transmitter – integrated delay)

Data to clock input setup (at receiver – integrated delay)

TholdR

Tcyc (1000Base-T)

Tcyc (100Base-TX)

Tcyc (10Base-T)

Clock to data input hold (at receiver – integrated delay)

Clock cycle duration for 1000Base-T

Clock cycle duration for 100Base-TX

Clock cycle duration for 10Base-T

Min. Typ. Max. Unit

–500

500

ps

1.0

2.6

ns

1.2

2.0

ns

1.2

2.0

ns

1.0

2.0

ns

1.0

2.0

ns

7.2

8

8.8

ns

36

40

44

ns

360 400 440

ns

The RGMII Version 2.0 Specification defines the RGMII data-to-clock skews only for 1000Mbps operation, which uses

both clock edges for sampling the data and control signals at the 125MHz clock frequency (8ns period). For 10/100Mbps

operations, the data signals are sampled on the rising clock edge and the control signals are sampled on both clock

edges. With slower clock frequencies, 2.5MHz (400ns period) for 10Mbps and 25MHz (40ns period) for 100Mbps, the

RGMII data-to-clock skews for 10/100Mbps operations will have greater timing margins than for 1000Mbps operation, and

therefore can be relaxed from 2.6ns (maximum) for 1000Mbps to 160ns (maximum) for 10Mbps and 16ns (maximum) for

100Mbps.

May 14, 2015

71

Revision 2.2

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