FIGURE 7-4:
MDC/MDIO TIMING
KSZ9031RNX
TABLE 7-3: MDC/MDIO TIMING PARAMETERS
Timing
Parameter
Description
Min. Typ. Max. Units
tP
tMD1
tMD2
tMD3
MDC period
MDIO (PHY input) setup to rising edge of MDC
MDIO (PHY input) hold from rising edge of MDC
MDIO (PHY output) delay from rising edge of MDC
120 400
—
10
—
—
10
—
—
ns
0
—
—
The typical MDC clock frequency is 2.5 MHz (400 ns clock period).
The KSZ9031RNX can operate with MDC clock frequencies generated from bit banging with GPIO pin in the 10s/100s
of Hertz and have been tested up to a MDC clock frequency of 8.33 MHz (120 ns clock period). Test condition for
8.33 MHz is for one KSZ9031RNX PHY on the MDIO line with a 1.0 kΩ pull-up to the DVDDH supply rail.
2016 Microchip Technology Inc.
DS00002117C-page 61