CDP68HC68T1 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
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CDP68HC68T1 Datasheet PDF : 24 Pages
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CDP68HC68T1
Functional Description
The Serial Peripheral Interface (SPI) utilized by the
CDP68HC68T1 is a serial synchronous bus for address and
data transfers. The clock, which is generated by the
microcomputer is active only during address and data
transfers. In systems using the CDP68HC05C4 or
CDP68HC05D2, the inactive clock polarity is determined by
the CPOL bit in the microcomputer’s Control Register. A
unique feature of the CDP68HC68T1 is that it automatically
determines the level of the inactive clock by sampling SCK
when CE becomes active (see Figure 8). Input data (MOSI)
is latched internally on the internal strobe edge and output
data (MISO) is shifted out on the shift edge, as defined by
Figure 8. There is one clock for each data bit transferred
(address, as well as data bits are transferred in groups of 8).
CPOL = 1
CE
SCK
INTERNAL
SHIFT STROBE
CPOL = 0
CE
SCK
INTERNAL
SHIFT STROBE
Address and Data Format
There are three types of serial transfer:
1. Address Control - Figure 9.
2. READ or WRITE Data - Figure 10.
3. Watchdog Reset (actually a non-transfer) Figure 11.
The Address/Control and Data bytes are shifted MSB first,
Into the serial data input (MOSI) and out of the serial data
output (MISO).
Any transfer of data requires an Address/Control byte to
specify a Write or Read operation and to select a Clock or
RAM location, followed by one or more bytes of data.
Data is transferred out of MISO for a Read and into MOSI for
a Write operation.
Address/Control Byte - (see Figure 9)
It is always the first byte received after CE goes true. To
transmit a new address, CE must first go false and then true
again. Bit 5 is used to select between Clock and RAM
locations.
MOSI
MSB
MSB -1
NOTE: “CPOL” is a bit that is set in the microcomputer’s Control
Register.
FIGURE 8. SERIAL RAM CLOCK (SCK) AS A FUNCTION OF
MCU CLOCK POLARITY (CPOL)
BIT
04
5
6
7
7
6
W/R
0
A0 through A4
CLK RAM
0
W/R
5
CLK RAM
4
3
2
1
0
A4
A3
A2
A1
A0
Selects 5-bit HEX Address of RAM or specifies Clock Register. Most Significant Address
Bit. If equal to “1”, A0 through A4 selects a Clock Register. If equal to “0”, A0 through A4
selects one of 32 RAM locations. Must be set to ”0” when not in Test Mode 7W/R W/R = “1”
initiates one or more WRITE cycles.W/R = “0”, initiates one or more READ cycles.
CE
SCK (NOTE)
MOSI
W/R
0
CLOCK
RAM
A4
A3
A2
A1
A0
NOTE: SCK can be either polarity.
FIGURE 9. ADDRESS/CONTROL BYTE-TRANSFER WAVEFORMS
FN1547 Rev 9.00
Decemember 8, 2015
Page 14 of 24
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