IDT7016L25GB8 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT7016L25GB8

HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

ing to gain control of the resource after the left processor, it would

read back a one in response to the zero it had attempted to write into

Semaphore 0. At this point, the software could choose to try and gain

control of the second 8K section by writing, then reading a zero into

Semaphore 1. If it succeeded in gaining control, it would lock out the

left side.

Once the left side was finished with its task, it would write a one to

Semaphore 0 and may then try to gain access to Semaphore 1. If

Semaphore 1 was still occupied by the right side, the left side could

undo its semaphore request and perform other tasks until it was able

to write, then read a zero into Semaphore 1. If the right processor

performs a similar task with Semaphore 0, this protocol would allow

the two processors to swap 8K blocks of Dual-Port RAM with each

other.

The blocks do not have to be any particular size and can even

be variable, depending upon the complexity of the software using the

semaphore flags. All eight semaphores could be used to divide the

Dual-Port RAM or other shared resources into eight parts. Sema-

phores can even be assigned different meanings on different sides

rather than being given a common meaning as was shown in the

example above.

Semaphores are a useful form of arbitration in systems like disk

Military, Industrial and Commercial Temperature Ranges

interfaces where the CPU must be locked out of a section of memory

during a transfer and the I/O device cannot tolerate any wait states.

With the use of semaphores, once the two devices has determined

which memory area was “off-limits” to the CPU, both the CPU and the

I/O devices could access their assigned portions of memory con-

tinuously without any wait states.

Semaphores are also useful in applications where no memory

“WAIT” state is available on one or both sides. Once a semaphore

handshake has been performed, both processors can access their

assigned RAM segments at full speed.

Another application is in the area of complex data structures. In

this case, block arbitration is very important. For this application one

processor may be responsible for building and updating a data

structure. The other processor then reads and interprets that data

structure. If the interpreting processor reads an incomplete data

structure, a major error condition may exist. Therefore, some sort

of arbitration must be used between the two different processors. The

building processor arbitrates for the block, locks it and then is able

to go in and update the data structure. When the update is com-

pleted, the data structure block is released. This allows the interpret-

ing processor to come back and read the complete data structure,

thereby guaranteeing a consistent data structure.

L PORT

SEMAPHORE

REQUEST FLIP FLOP

D0

D

Q

WRITE

R PORT

SEMAPHORE

REQUEST FLIP FLOP

Q

D

D0

WRITE

SEMAPHORE

READ

SEMAPHORE

READ

,

3190 drw 20

Figure 4. IDT7016 Semaphore Logic

6.1492

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