AD5262BRUZ200 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD5262BRUZ200 Datasheet PDF : 24 Pages
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AD5260/AD5262
Parameter
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
Crosstalk 11
Analog Crosstalk
Resistor Noise Voltage
INTERFACE TIMING CHARACTERISTICS6, 12
Clock Frequency
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay13
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
Symbol
BW
THDW
tS
CT
CTA
eN_WB
fCLK
tCH, tCL
tDS
tDH
tPD
tCSS
tCSW
tRS
tCSH
tCS1
Conditions
Min Typ1
Max Unit
RAB = 20 kΩ/50 kΩ/200 kΩ
VA = 1 VRMS, VB = 0 V, f = 1 kHz,
RAB = 20 kΩ
VA = +5 V, VB = −5 V, ±1 LSB
error band, RAB = 20 kΩ
VA = VDD, VB = 0 V, measure VW
with adjacent RDAC making
full-scale code change (AD5262
only)
VA1 = VDD, VB1 = 0 V, measure VW1
with VW2 = 5 V p-p at f = 10 kHz,
RAB = 20 kΩ/200 kΩ (AD5262
only)
RWB = 20 kΩ, f = 1 kHz
Specifications apply to all parts
Clock level high or low
20
10
10
RL = 1 kΩ, CL< 20 pF
1
5
20
50
0
10
310/130/30
0.014
5
1
kHz
%
μs
nV-sec
–64
dB
13
nV/√Hz
25 MHz
ns
ns
ns
160 ns
ns
ns
ns
ns
ns
1 Typical values represent average readings at 25°C and VDD = +5 V, VSS = −5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and
VSS = −5V.
3 VAB = VDD, wiper = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.
8 Worst-case supply current consumed when all logic-input levels set at 2.4 V, which is the standard characteristic of CMOS logic.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All dynamic characteristics use VDD = +5 V, VSS = −5 V, VL = +5 V.
11 Measured at VW where an adjacent VW is making a full-scale voltage change.
12 See Figure 5 for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using VL = 5 V.
13 Propagation delay depends on value of VDD, RL, and CL.
Rev. A | Page 4 of 24
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