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100351PC View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
Manufacturer
100351PC
Fairchild
Fairchild Semiconductor Fairchild
100351PC Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
Commercial Version (Continued)
SOIC and PLCC AC Electrical Characteristics
VEE = −4.2V to 5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = 0°C
Min
Max
TC = +25°C
Min
Max
TC = +85°C
Min
Max
Units
Conditions
fMAX
tPLH
tPHL
tPLH
tPHL
tTLH
tTHL
tS
Toggle Frequency
Propagation Delay
CPa, CPb to Output
Propagation Delay
MR to Output
Transition Time
20% to 80%, 80% to 20%
Setup Time
D0D5
MR (Release Time)
375
0.80
1.10
0.45
1.80
2.10
1.70
375
0.80
1.10
0.45
1.80
2.10
1.60
375
0.90
1.20
0.45
1.90
2.20
1.70
MHz Figures 2, 3
ns Figures 1, 3
ns Figures 1, 4
ns Figures 1, 3
0.30
1.50
0.30
1.50
0.30
1.50
ns Figure 5
Figure 4
tH
tPW(H)
tOSHL
Hold Time
D0D5
Pulse Width HIGH
CPa, CPb, MR
Maximum Skew Common Edge
Output-to-Output Variation
0.80
2.00
0.80
2.00
0.80
2.00
220
220
220
ns Figure 5
ns Figures 3, 4
PLCC only
ps (Note 4)
Clock to Output Path
tOSLH
Maximum Skew Common Edge
Output-to-Output Variation
PLCC only
210
210
210
ps (Note 4)
Clock to Output Path
tOST
Maximum Skew Opposite Edge
Output-to-Output Variation
PLCC only
240
240
240
ps (Note 4)
Clock to Output Path
tPS
Maximum Skew
Pin (Signal) Transition Variation
PLCC only
230
230
230
ps (Note 4)
Clock to Output Path
Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-
aged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite
directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design.
www.fairchildsemi.com
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