CL3128ATC100-10 View Datasheet(PDF) - Clear Logic
Part Name
Description
Manufacturer
CL3128ATC100-10 Datasheet PDF : 14 Pages
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CL3128A Laser Processed Logic Devices
AC Electrical Specifications cont.
Internal Timing Parameters[4]
Symbol
Parameter
Conditions
tiN
Input pad and buffer delay
tIO I/O input pad and buffer delay
tSEXP Shared expander delay
tPEXP Parallel expander delay
tLAD Logic array delay
tLAC Logic control array delay
tIOE Internal output enable delay
tOD1 Output buffer and pad delay
CL = 35 pF
Slow slew rate = off, VCCIO = 5.0 V
tOD2 Output buffer and pad delay
CL = 35 pF
Slow slew rate = off, VCCIO = 3.3 V
Output buffer and pad delay
tOD3 Slow slew rate = on,
CL = 35 pF
VCCIO = 5.0 V or 3.3 V
tZX1
Output buffer enable delay
Slow slew rate = off, VCCIO = 5.0 V
CL = 35 pF
tZX2 Output buffer enable delay
CL = 35 pF
Slow slew rate = off, VCCIO = 3.3 V
Output buffer enable delay
tZX3 Slow slew rate = on,
CL = 35 pF
VCCIO = 5.0 V or 3.3 V
tXZ Output buffer disable delay
CL = 5 pF[3]
tSU Register setup time
tH
Register hold time
tRD Register delay
tCOMB Combinatorial delay
tIC
Array clock delay
tEN Register enable time
tGLOB Global control delay
tPRE Register preset time
tCLR Register clear time
tLIA LIA delay
Speed: -7
Min
Max
0.4
0.4
3.6
0.8
3.7
3.4
0.0
0.6
1.1
5.6
4.0
4.5
9.0
4.0
1.3
2.4
2.1
1.5
3.4
3.4
1.4
3.9
3.9
1.3
Speed: -10
Min
Max
0.6
0.6
4.9
1.1
5.0
4.6
0.0
0.7
1.2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.7
ns
5.0
ns
5.5
ns
10.0
ns
5.0
ns
1.7
ns
3.8
ns
2.8
ns
2.0
ns
4.6
ns
4.6
ns
1.8
ns
5.2
ns
5.2
ns
1.7
ns
3KA tbl 07A2
Page 11
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