A3V56S30ETP View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

A3V56S30ETP

256M Single Data Rate Synchronous DRAM

Unspecified 

A3V56S30ETP

A3V56S40ETP

256M Single Data Rate Synchronous DRAM

Pin Descriptions

SYMBOL

TYPE

DESCRIPTION

CLK

CKE

Input

Input

Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive

edge of CLK. CLK also increments the internal burst counter and controls the output registers.

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the

clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle),

ACTIVE POWER-DOWN (row active in any bank), DEEP POWER DOWN (all banks idle), or

CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the

device enters power-down and self refresh modes, where CKE becomes asynchronous until

after exiting the same mode. The input buffers, including CLK, are disabled during power-down

and self refresh modes, providing low standby power. CKE may be tied HIGH.

Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when /CS is registered HIGH. /CS provides for external

/CS

Input

bank selection on systems with multiple banks. /CS is considered part of the command code.

/CAS,

/RAS,

/WE

DQM,

DQML,

DQMU,

Input

Input

Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered.

Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an

output enable signal for read accesses. Input data is masked during a WRITE cycle. The output

buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. DQM

corresponds to DQ0–DQ7 (A3V56S30ETP). DQML corresponds to DQ0–DQ7, DQMU

corresponds to DQ8–DQ15 (A3V56S40ETP).

BA0, BA1

Input

Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or

PRECHARGE command is being applied. These pins also select between the mode register and

the extended mode register.

A0–A12

Input

A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is

specified by A0-12. The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also

used to indicate precharge option. When A10 is high at a read / write command, an auto

precharge is performed. When A10 is high at a precharge command, all banks are precharged.

Data Input/Output: Data bus.

DQ0–DQ15

I/O

Internally Not Connected: These could be left unconnected, but it is recommended they be

NC

–

connected or VSS.

VDDQ

VSSQ

VDD

VSS

Supply

Supply

Supply

Supply

DQ Power: Provide isolated power to DQs for improved noise immunity.

DQ Ground: Provide isolated ground to DQs for improved noise immunity.

Core Power Supply.

Ground.

Revision 2.2

Page 4/39

Mar., 2009

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