JTS8388B-1V1B View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

JTS8388B-1V1B

ADC 8-bit 1 Gsps

Unspecified 

4. Functional Description

4.1 Block Diagram

The following figure shows the simplified block diagram.

Figure 4-1. Simplified Block Diagram

GAIN

TS8388B

VIN, VINB

MASTER/SLAVE TRACK & HOLD AMPLIFIER

G=2

T/H

G=1

T/H

G=1

RESISTOR

CHAIN

ANALOG

ENCODING

BLOCK

4

4

INTERPOLATION

STAGES

5

CLK, CLKB

CLOCK

BUFFER

DRRB DR, DRB

GORB

REGENERATION

LATCHES

4

5

ERROR CORRECTION &

DECODE LOGIC

8

OUTPUT LATCHES &

BUFFERS

8

DATA, DATAB OR, ORB

4.2 Functional Description

The TS8388B is an 8-bit 1 Gsps ADC based on an advanced high-speed bipolar technology featuring a

cutoff frequency of 25 GHz.

The TS8388B includes a front-end master/slave Track and Hold stage (S/H), followed by an analog

encoding stage and interpolation circuitry.

Successive banks of latches regenerate the analog residues into logical data before entering an error

correction circuitry and a resynchronization stage followed by 75Ω differential output buffers.

The TS8388B works in fully differential mode from analog inputs up to digital outputs.

The TS8388B features a full-power input bandwidth of 1.5 GHz.

A control pin GORB is provided to select either Gray or Binary data output format.

A gain control pin is provided in order to adjust the ADC gain.

A Data Ready output asynchronous reset (DRRB) is available on TS8388B.

The TS8388B uses only vertical isolated NPN transistors together with oxide isolated polysilicon resis-

tors, which allow enhanced radiation tolerance (no performance drift measured at 150 kRad total dose).

2

0860F–BDC–12/09

e2v semiconductors SAS 2009

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