JTS8388B-1V1B View Datasheet(PDF) - Unspecified
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JTS8388B-1V1B Datasheet PDF : 62 Pages
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TS8388B
Table 5-3. Electrical Specifications (Continued)
Parameter
Test
Value
Symbol
Level
Min
Typ
Max
Total Harmonic Distortion
–
–
–
–
FS = 1 Gsps, FIN = 20 MHz
FS = 1 Gsps, FIN = 500 MHz
FS = 1 Gsps, FIN = 1000 MHz (–1 dBFs)
FS = 50 Msps, FIN = 25 MHz
Spurious Free Dynamic Range
4
50
54
–
THD
4
46
50
–
4
42
46
–
1, 2, 6
46
45
–
–
–
–
–
FS = 1 Gsps, FIN = 20 MHz
4
52
57
–
FS = 1 Gsps, FIN = 500 MHz
FS = 1 Gsps, FIN = 1000 MHz (–1 dBFs)
4
47
52
–
SFDR
4
42
47
–
FS = 1 Gsps, FIN = 1000 MHz (–3 dBFs)
4
45
50
–
FS = 50 Msps, FIN = 25 MHz
1, 2, 6
40
54
–
Two-tone Intermodulation Distortion
4
–
–
–
FIN1 = 489 MHz at FS = 1 Gsps
FIN2 = 490 MHz at FS = 1 Gsps
IMD
–
–47
–52
–
Switching Performance and Characteristics – See Figure 5-1 and Figure 5-2 on page 10
Maximum clock frequency
Minimum clock frequency
Minimum Clock pulse width (high)
FS
–
1
–
1.4
FS
4
10
–
50
TC1
4
0.280
0.500
50
Minimum Clock pulse width (low)
TC2
4
0.350
0.500
50
Aperture delay
Aperture uncertainty
TA
Jitter
4
100
+250
400
4
–
0.4
0.6
Data output delay
TDO
4
1150
1360
1660
Output rise/fall time for DATA (20% to 80%)
Output rise/fall time for DATA READY (20% to 80%)
TR/TF
TR/TF
4
250
350
550
4
250
350
550
Data ready output delay
TDR
4
1110
1320
1620
Data ready reset delay
TRDR
4
–
720
1000
Data to data ready – Clock low pulse width
(See “Timing Diagrams” on page 10.)
TOD-TDR
4
0
40
80
Data to data ready output delay (50% duty cycle) at
1 Gsps (See “Timing Diagrams” on page 10.)
TD1
4
420
460
500
Data pipeline delay
TPD
4
4
Notes: 1. Differential output buffers are internally loaded by 75Ω resistors. Buffer bias current = 11 mA.
Unit
–
dB
dB
dB
dB
–
dBc
dBc
dBc
dBc
dBc
–
dBc
Note
(2)
(2)
(2)
Gsps
Msps
ns
ns
ps
ps (rms)
ps
(14)
(15)
(2)
(2)(5)
(2)(10)
(11)(12
)
ps
(11)
ps
(11)
(2)(10)
ps
(11)(12
)
ps
(9)(13)
ps
(14)
ps
clock
cycles
(2)(15)
8
0860F–BDC–12/09
e2v semiconductors SAS 2009
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