PIC32MX View Datasheet(PDF) - Microchip Technology
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PIC32MX Datasheet PDF : 321 Pages
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PIC32MX1XX/2XX
The MIPS architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the pri-
mary register file instead of the HI/LO register pair. By
avoiding the explicit MFLO instruction required when
using the LO register, and by supporting multiple desti-
nation registers, the throughput of multiply-intensive
operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
3.2.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configura-
tion information, such as presence of options like
MIPS16e, is also available by accessing the CP0
registers, listed in Table 3-2.
TABLE 3-2: COPROCESSOR 0 REGISTERS
Register
Number
Register
Name
Function
0-6
7
8
9
10
11
12
12
12
12
13
14
15
15
16
16
16
16
17-22
23
24
25-29
30
31
Note 1:
2:
Reserved
Reserved in the PIC32MX1XX/2XX family core.
HWREna
BadVAddr(1)
Count(1)
Enables access via the RDHWR instruction to selected hardware registers.
Reports the address for the most recent address-related exception.
Processor cycle count.
Reserved
Compare(1)
Status(1)
IntCtl(1)
SRSCtl(1)
SRSMap(1)
Cause(1)
EPC(1)
Reserved in the PIC32MX1XX/2XX family core.
Timer interrupt control.
Processor status and control.
Interrupt system status and control.
Shadow register set status and control.
Provides mapping from vectored interrupt to a shadow set.
Cause of last general exception.
Program counter at last exception.
PRId
Processor identification and revision.
EBASE
Exception vector base register.
Config
Configuration register.
Config1
Configuration Register 1.
Config2
Configuration Register 2.
Config3
Configuration Register 3.
Reserved
Debug(2)
DEPC(2)
Reserved in the PIC32MX1XX/2XX family core.
Debug control and exception status.
Program counter at last debug exception.
Reserved
ErrorEPC(1)
DESAVE(2)
Reserved in the PIC32MX1XX/2XX family core.
Program counter at last error.
Debug handler scratchpad register.
Registers used in exception processing.
Registers used during debug.
© 2011 Microchip Technology Inc.
Preliminary
DS61168C-page 35
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