LC74781M View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
Manufacturer
LC74781M Datasheet PDF : 16 Pages
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LC74781, 74781M
COMMAND3 (Horizontal display start position and horizontal character size setup command)
First byte
DA0 to DA7
7
6
5
4
3
2
1
0
Register name
—
—
—
—
HS21
HS20
HS11
HS10
State
1
0
1
1
0
1
0
1
0
1
0
1
Register content
Function
Command 3 identification code
Set the horizontal display start position and horizontal
character size.
HS21
HS20
0
0
1 Tc per dot
1
3 Tc per dot
HS11
HS10
0
0
1 Tc per dot
1
3 Tc per dot
1
2 Tc per dot
1 Tc per dot
1
2 Tc per dot
1 Tc per dot
Note
Second line horizontal character size
First line horizontal character size
Second byte
DA0 to DA7 Register name
State
Register content
Function
7
—
0 Second byte identification bit
0 An LC oscillator is used for the dot clock.
6
LC
1 A crystal oscillator is used for the dot clock.
5
HP5
(MSB)
0
If HS is the horizontal start position then:
1
0
HS
=
Tc
×
5
(2Σ
2nHPn)
n=0
4
HP4
1
Tc: Period of the oscillator connected to OSCIN/OSCOUT in
0
operating mode.
3
HP3
1
0
2
HP2
1
0
1
HP1
1
0
HP0
0
(LSB)
1
Note: The register states are all set to zero when the LC74781/M is reset with the RST pin.
COMMAND4 (Display control setup command)
First byte
DA0 to DA7
7
6
5
4
3
2
1
0
Register name
—
—
—
—
TSTMOD
RAMERS
OSCSTP
SYSRST
State
1
1
0
0
0
1
Register content
Function
Command 4 identification code
Display control
Normal operating mode
Test mode
0
1 Erase display RAM (set to 7F hexadecimal)
0 Do not stop the crystal oscillator and LC oscillator circuits.
1 Stop the crystal oscillator and LC oscillator circuits.
0
1 Reset all registers and turn the display off.
Note
Selects the dot clock used in horizontal
character display.
The horizontal display start position is
set by the six bits HP5 to HP0.
The weight of bit 1 is 2Tc.
Note
This bit must be zero.
The RAM erase operation requires about
500 µs (It is executed in the DSPOFF
state.)
Valid when character display is off in
external synchronization mode.
Reset occurs when the CS pin is low, and
the reset is cleared when CS goes high.
No. 4988-10/16
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