MEC1404 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

MEC1404

Keyboard and Embedded Controller Products for Notebook PC

Microchip Technology 

MEC140X/1X

Keyboard and Embedded Controller Products for

Notebook PC

Common Features

• 3.3V Operation

• ACPI 3.0 Compliant

• PC2001 compliant

• VTR (standby) and VBAT Power Planes

- Low Standby Current in Sleep Mode

• Connected Standby Support

• 32kHz Clock Source

- Internal 32kHz Oscillator

- External 32kHz Clock Source

- 32kHz Crystal (XTAL) Supported

- Single-Ended 32kHz Clock Source

• LPC Host Interface

- LPC Specification 1.1 Compatible

- LPC I/O and Memory Cycles Decoded

- Supports optional signals: CLKRUN#, LPCPD#,

SERIRQ, SMI#, EC_SCI# (ACPI PME Event)

- Supports 19.2 MHz to 33 MHz nominal bus clock

speeds

• Configuration Register Set

- Compatible with ISA Plug-and-Play Standard

- EC-Programmable Base Address

• 8042 Emulated Keyboard Controller

- 8042 Style Host Interface

- Port 92 Legacy A20M Support

- Fast GATEA20 & Fast CPU_RESET

• System to EC Message Interface

- One Embedded Memory Interface

- Host Serial or Parallel IRQ Source

- Provides Two Windows to On-Chip SRAM for

Host Access

- Two Register Mailbox Command Interface

- Mailbox Registers Interface

- Thirty-two 8-Bit Scratch Registers

- Two Register Mailbox Command Interface

- Two Register SMI Source Interface

- Five ACPI Embedded Controller Interfaces

- Four EC Interfaces

- One Power Management Interface

• MIPS32 M14K™ Microcontroller Core

- microMIPS-Compatible Instruction Set

- High-performance Multiply/Divide Unit

- Programmable clock frequencies: 48MHz,

12MHz, 3MHz, and 1MHz

- Sleep mode

- 2-wire Debug Interface (ICSP)

- 6 Breakpoints (4-instruction; 2-data)

- Enhanced to Support Debug in Heavy and

Deep Sleep States

• Trace FIFO Debug Port (TFDP)

• Internal DMA Controller

- Hardware or Firmware Flow Control

- Firmware Initiated Memory-to-Memory transfers

- 7-Hardware DMA Channels support three

SMBus Master/Slave Controllers and one SPI

Controller

- Hardware CRC-32 Generator on Channel 0

• Secure Boot ROM Loader

- 4 Code Images in Shared Flash Supported

- Crisis Recovery over Keyboard matrix Scan Pins

- Supports CRC-32 and AES-128 Encryption

• Vectored Interrupt Controller

- Maskable Interrupt controller

- Maskable Hardware Wake-Up Events

- Supports legacy aggregated mode

- Supports Vector Generation per Status Bit

• Programmable 16-bit Counter/Timer Interface

- Four 16-bit Auto-reloading Counter/Timer

Instances

- Two Operating Modes per Instance: Timer and

One-shot.

• 32-bit RTOS Timer

- Runs Off 32kHz Clock Source

- Continues Counting in all the Chip Sleep States

Regardless of Processor Sleep State

- Counter is Halted when Embedded Controller is

Halted (e.g., JTAG debugger active, break

points)

- Generates wake-capable interrupt event

• Watch Dog Timer (WDT)

• Hibernation Timer Interface

- One 32.768 KHz Driven Timer

- Programmable Wake-up from 0.5ms to 128 Min-

utes

• Week Timer

- System Power Present Input Pin

 2015 - 2016 Microchip Technology Inc.

DS00001956D-page 1

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