M-8888-01SM View Datasheet(PDF) - Clare Inc => IXYS

Part Name

Description

Manufacturer

M-8888-01SM

DTMF Transceiver

Clare Inc => IXYS 

M-8888

Single-Ended Input Configuration

Differential Input Configuration

Functional Description

M-8888 functions consist of a high-performance

DTMF receiver with an internal gain setting amplifier

and a DTMF generator that contains a tone burst

counter for generating precise tone bursts and paus-

es. The call progress mode, when selected, allows the

detection of call progress tones. A standard 8051,

8086/8 series microprocessor interface allows access

to an internal status register, two control registers, and

two data registers.

ing the amplifier inputs at VDD/2. Provisions are made

for the connection of a feedback resistor to the op-amp

output (GS) for gain adjustment. In a single-ended

configuration, the input pins should be connected as

shown in the Single-Ended Input Configuration above.

Differential Input Configuration above shows the nec-

essary connections for a differential input configura-

tion.

Input Configuration

The input arrangement consists of a differential input

operational amplifier and bias sources (VREF) for bias-

Receiver Section

The low and high group tones are separated by apply-

ing the DTMF signal to the inputs of two sixth-order

Pin Functions

Name

IN+

IN-

GS

VREF

VSS

OSC1

OSC2

TONE

WR

CS

RS0

RD

IRQ /CP

D0-D3

ESt

St/GT

VDD

Description

Noninverting op-amp input.

Inverting op-amp input.

Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor.

Reference voltage output. Nominally VDD/2 is used to bias inputs at mid-rail.

Negative power supply input.

DTMF clock/oscillator input.

Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit.

Dual tone multifrequency (DTMF) output.

Write input. A low on this pin when CS is low enables data transfer from the microprocessor. TTL compatible.

Chip select. TTL input (CS = 0 to select the chip).

Register select input. See Internal Register Functions on page 7. TTL compatible.

Read input. A low on this pin when CS is low enables data transfer to the microprocessor. TTL compatible..

Interrupt request to microprocessor (open-drain output). Also, when call progress (CP) mode has been selected and

interrupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the

input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Timing Diagrams on

page 11.

Microprocessor data bus. TTL compatible.

Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition).

Any momentary loss of signal condition will cause ESt to return to a logic low.

Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register

the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The

GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St.

Positive power supply input.

2

www.clare.com

Rev. 1

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