ISL6553 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
ISL6553 Datasheet PDF : 15 Pages
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ISL6553
becomes active slightly before the NMOS transistor pulls
.
“down”, generating the slight rise in the PGOOD voltage.
Note that Figure 5 shows the 12V gate driver voltage available
before the 5V supply to the ISL6553 has reached its threshold
level. If conditions were reversed and the 5V supply was to rise
first, the start-up sequence would be different. In this case the
ISL6553 will sense an over-current condition due to charging
the output capacitors. The supply will then restart and go
through the normal Soft-Start cycle.
12V ATX
SUPPLY
PGOOD
VCORE
DELAY TIME
PWM 1
OUTPUT
PGOOD
5 V ATX
SUPPLY
VIN = 5V, CORE LOAD CURRENT = 31A
FREQUENCY 200kHz
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
FIGURE 5. SUPPLY POWERED BY ATX SUPPLY
VCORE
5V
VCC
VIN = 12V
FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING AT
500kHz
DELAY TIME
V COMP
PGOOD
VCORE
5V
VCC
VIN = 12V
FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING AT
200kHz
Fault Protection
The ISL6553 protects the microprocessor and the entire power
system from damaging stress levels. Within the ISL6553 both
over-voltage and over-current circuits are incorporated to
protect the load and regulator.
Over-Voltage
The VSEN pin is connected to the microprocessor CORE
voltage. A CORE over-voltage condition is detected when the
VSEN pin goes more than 15% above the programmed VID
level.
The over-voltage condition is latched, disabling normal PWM
operation, and causing PGOOD to go low. The latch can only
be reset by lowering and returning VCC high to initiate a POR
and Soft-Start sequence.
During a latched over-voltage, the PWM outputs will be driven
either low or three state, depending upon the VSEN input.
PWM outputs are driven low when the VSEN pin detects that
the CORE voltage is 15% above the programmed VID level.
This condition drives the PWM outputs low, resulting in the
lower or synchronous rectifier MOSFETs to conduct and shunt
the CORE voltage to ground to protect the load.
If after this event, the CORE voltage falls below the over-
voltage limit (plus some hysteresis), the PWM outputs will
three state. The HIP6601 family drivers pass the three state
information along, and shuts off both upper and lower
MOSFETs. This prevents “dumping” of the output capacitors
back through the lower MOSFETs, avoiding a possibly
destructive ringing of the capacitors and output inductors. If the
conditions that caused the over-voltage still persist, the PWM
outputs will be cycled between three state and VCORE
clamped to ground, as a hysteretic shunt regulator.
FN4931 Rev 1.00
August 2004
Page 8 of 15
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