HM658512A View Datasheet(PDF) - Hitachi -> Renesas Electronics
Part Name
Description
Manufacturer
HM658512A Datasheet PDF : 22 Pages
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HM658512A Series
Pin Functions
CE: Chip Enable (Input)
CE is a basic clock. RAM is active when CE is low, and is on standby when CE is high.
A0 to A18: Address Inputs (Input)
A0 to A10 are row addresses and A11 to A18 are column addresses. The entire addresses A0 to A18
are fetched into RAM by the falling edge of CE.
OE/RFSH: Output Enable/Refresh (Input)
This pin has two functions. Basically it works as OE when CE is low, and as RFSH when CE is high
(in standby mode). After a read or write cycle finishes, refresh does not start if CE goes high while
OE/RFSH is held low. In order to start a refresh in standby mode, OE/RFSH must go high to reset the
refresh circuits of the RAM. After the refresh circuits are reset, the refresh starts when OE/RFSH goes
low.
I/O0 to I/O7: Input/Output (Inputs and Outputs) These pins are data I/O pins.
WE: Write Enable (Input)
RAM is in write mode when WE is low, and is in read mode when WE is high. I/O data is fetched into
RAM by the rising edge of WE or CE (earlier timing) and the data is written into memory cells.
Refresh
There are three refresh modes : address refresh, automatic refresh and self refresh.
(1) Address refresh: Data is refreshed by accessing all 2048 row addresses every 32 ms. A read is one
method of accessing those addresses. Each row address (2048 addresses of A0 to A10)must be read at
least once every 32 ms. In address refresh mode, OE/RFSH can remain high. In this case, the I/O pins
remain at high impedance, but the refresh is done within RAM.
(2) Automatic refresh: Instead of address refresh, automatic refresh can be used. RAM goes to automatic
refresh mode if OE/RFSH falls while CE is high and it remains low for at least tFAP. One automatic
refresh cycle is executed by one low pulse of OE/RFSH. It is not necessary to input the refresh
address from outside since it is generated internally by an on-chip address counter. 2048 automatic
refresh cycles must be done every 32 ms.
(3) Self refresh: Self refresh mode is suitable for data retention by battery. In standby mode, a self refresh
starts automatically when OE/RFSH stays low for more than 8 µs. Refresh addresses are automatically
specified by the on-chip address counter, and the refresh period is determined by the on-chip timer.
Automatic refresh and self refresh are distinguished from each other by the width of the OE/RFSH low
pulse in standby mode. If the OE/RFSH low pulse is wider than 8 µs, RAM becomes into self refresh
mode; if the OE/RFSH low pulse is less than 8 µs, it is recognized as an automatic refresh instruction.
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