LC75893M View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
Manufacturer
LC75893M Datasheet PDF : 23 Pages
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Serial Data Output
1. When CL is stopped at the low level
LC75893M
Note: B0 to B3 and A0 to A3 ············ CCB address
2. When CL is stopped at the high level
Output data
Output data
Note: B0 to B3 and A0 to A3 ··········· CCB address
• CCB address·········· 43H
• KD1 to KD20 ·········· Key data
• SA ·························· Sleep acknowledge data
Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD20) and sleep
acknowledge data (SA) will be invalid.
Output Data
1.KD1 to KD20 : Key data
When a key matrix of up to 20 keys is formed from the KS1 to KS4 output pins and the KI1 to KI5 input pins and one
of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship
between those pins and the key data bits.
KS1/S15
KS2/S16
KS3
KS4
KI1
KD1
KD6
KD11
KD16
KI2
KD2
KD7
KD12
KD17
KI3
KD3
KD8
KD13
KD18
KI4
KD4
KD9
KD14
KD19
KI5
KD5
KD10
KD15
KD20
When the KS1/S15 and KS2/S16 output pins are selected to be segment outputs by control data bits K0 and K1 and a
key matrix of up to 10 keys is formed using the KS3 and KS4 output pins and the KI1 to KI5 input pins, the KD1 to
KD10 key data bits will be set to 0.
2.SA: Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is
input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep
mode and 0 in normal mode.
Sleep Mode Functions
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common
outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces
power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the
S1/P1 to S4/P4 outputs can be used as general-purpose output ports according to the state of the P0 to P2 control data
bits, even in sleep mode. (See the control data description for details.)
No. 5971-10/23
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