STK14C88-W20I View Datasheet(PDF) - Simtek Corporation
Part Name
Description
Manufacturer
STK14C88-W20I Datasheet PDF : 12 Pages
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STK14C88
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V ± 10%)b, f
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
STK14C88-20 STK14C88-25 STK14C88-35 STK14C88-45
UNITS
MIN MAX MIN MAX MIN MAX MIN MAX
12
tAVAV
13
tWLWH
14
tELWH
15
tDVWH
16
tWHDX
17
tAVWH
18
tAVWL
19
tWHAX
20
tWLQZj, k
21
tWHQX
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
tWC Write Cycle Time
20
25
35
45
ns
tWP Write Pulse Width
15
20
25
30
ns
tCW Chip Enable to End of Write
15
20
25
30
ns
tDW Data Set-up to End of Write
8
10
12
15
ns
tDH Data Hold after End of Write
0
0
0
0
ns
tAW Address Set-up to End of Write
15
20
25
30
ns
tAS Address Set-up to Start of Write
0
0
0
0
ns
tWR Address Hold after End of Write
0
0
0
0
ns
tWZ Write Enable to Output Disable
7
10
13
15
ns
tOW Output Active after End of Write
5
5
5
5
ns
Note k: If W is low when E goes low, the outputs remain in the high-impedance state.
Note l: E or W must be ≥ VIH during address transitions.
Note m: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledl, m
ADDRESS
12
tAVAV
14
tELWH
E
19
tWHAX
W
DATA IN
DATA OUT
18
tAVWL
17
tAVWH
13
tWLWH
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
16
tWHDX
21
tWHQX
SRAM WRITE CYCLE #2: E Controlledl, m
ADDRESS
12
tAVAV
18
tAVEL
14
tELEH
19
tEHAX
E
W
DATA IN
DATA OUT
17
tAVEH
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
16
tEHDX
July 1999
5-24
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