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LC66558B View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
Manufacturer
LC66558B Datasheet PDF : 22 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC66556B, 66558B
Continued from preceding page.
Parameter
Symbol
Conditions
min
[Serial clock]
Cycle time
Input
Output
Low level/high Input
level pulse widths Output
Rise/fall times Output
[Serial input]
0.9
tCKCY
2.0
tCKL
SCK0, SCK1: With the timing from Figure 4 and
the test load from Figure 5
0.4
tCKH
1.0
tCKR, tCKF
Data setup time
Data hold time
tICK
S10, SI1, SI0, SI1: With the timing in Figure 4.
0.3
Stipulated with respect to the rising edge
tCKI
for SCK0 and SCK1.
0.3
[Serial output]
Output delay time
tCKO
SO0, SO1: With the timing from Figure 5 and
the test load from Figure 5. Stipulated with respect to
the falling edge for SCK0 and SCK1.
[Pulse input conditions]
INT0, See Figure 6:
INT0
Conditions such that the INT0 interrupt is accepted
High and low level pulse widths tI0H, tI0L Conditions such that timer 0 event counter and pulse
2
width measurement inputs are accepted
High and low level pulse widths for
INT1, INT2, INT3, INT4, INT5, See Figure 6:
interrupt inputs other than INT0
tI1H, tI1L Conditions such that all interrupts are accepted
2
PIN1
PIN1, See Figure 6: Conditions such that timer 1
High and low level pulse widths tPINH, tPINL event counter inputs are accepted
2
RES
RES, See Figure 6: Conditions such that reset
High and low level pulse widths tRSH, tRSL can occur
3
Comparator response speed
Operating mode current drain
HALT mode current drain
Hold mode current drain
Note: 8. Reset state
TRS
IDD op
IDDHALT
IDDHOLD
PD, See Figure 7
VDD: 4 MHz ceramic oscillator
VDD: 4 MHz external clock
VDD: 4 MHz ceramic oscillator
VDD: 4 MHz external clock
VDD: VDD = 1.8 to 5.5 V
typ
max
Unit Note
µs
TCYC
µs
TCYC
0.1
µs
µs
µs
0.3
µs
TCYC
TCYC
TCYC
TCYC
20
ms
3.0
5.0
mA
8
3.0
5.0
mA
1.0
2.0
mA
1.0
2.0
mA
0.01
10
µA
Figure 1 External Clock Input Waveform
Figure 2 Ceramic Oscillator Circuit
Figure 3 Oscillator Stabilization Period
No. 5003-10/22

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