CY7C197B View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C197B Datasheet PDF : 10 Pages
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Features
• Fast access time: 12 ns and 25 ns
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
• CMOS for optimum speed/power
• TTL-compatible Inputs and Outputs
• Available in 24 DIP and 24 SOJ
Logic Block Diagram
Input
Buffer
CY7C197B
256 Kb (256K x 1) Static RAM
General Description1
The CY7C197B is a high-performance CMOS Asynchronous
SRAM organized as 256K × 1 bits that supports an
asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected.
See the Truth Table in this data sheet for a complete
description of read and write modes.
The CY7C197B is available in 24 DIP and 24 SOJ package(s).
Din
RAM
Array
Dout
Column
Decoder
Power
Down
Circuit
CE
WE
x Ax
Product Portfolio
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
12 ns
12
150
10
25 ns
Unit
25
ns
95
mA
10
mA
Notes:
1. For best-practice recommendations, please refer to the Cypress application note System Design Guidelines at www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05410 Rev. **
Revised September 15, 2003
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