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ADM9240 View Datasheet(PDF) - ON Semiconductor

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ADM9240 Datasheet PDF : 22 Pages
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ADM9240
Table XV. Register 48h, Serial Address Register (Power-On Default = 0010 11(A1)(A0))
Bit
Name
R/W
Description
0–6
Serial Bus Address Read/Write Serial Bus Address (Bits 0 and 1 are Set by A0, A1 and Bit 7 is Read Only)
Table XVI. Register 49h, VID 4/Device ID Register (Power-On Default 1000000(VID4))
Bit
Name
R/W
Description
0
VID4
1–7
Reserved
Read
Read/Write
VID4 Input from Pentium®
Table XVII. Register 4Bh, Temperature Configuration Register (Power-On Default = 01h)
Bit Name
R/W
Description
0–1 Hot Temperature Read/Write If Bit 0 and Bit 1 of this register are both zero or one, this selects the default
Interrupt Mode
interrupt mode, which gives the user an interrupt if the temperature goes above
Select Bits
the hot limit. The interrupt will be cleared once the status register is read, but it
will again be generated when the next conversion has completed. It will continue to
do so until the temperature goes below the hysteresis limit.
A 0 on Bit 1 and a 1 on Bit 0 selects the one-time interrupt mode, which gives the
user an interrupt when the temperature goes above the hot limit. The interrupt will
2–6 Reserved
Rea
be cleared once the status register is read. Another interrupt will not be generated
until the temperature first goes below the hysteresis limit. No more interrupts will
be generated until the temperature again goes above the hot limit. The correspond-
ing bit will be cleared in the status register every time it is read, but may not set
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A 1 on Bit 1 and a 0 on Bit 0 selects the comparator mode. This gives an INT
when the temperature exceeds the hot limit. This INT remains active until the
temperature goes below the hot limit (no hysteresis), when the INT will become
inactive.
2–6 Reserved
Read/Write Default = 00000
7
Temp
Read only LSB of Temperature Reading = 0.5°C
0–1 Hot Temperature Read
Bit Name
R
1–7
Reserved
Rea
Bit
Name
R
0–6
Serial Bus Address Rea
Bit
Name
R
Pentium is a registered trademark of Intel Corp.
REV. 0
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