DSP1627(2000) View Datasheet(PDF) - Agere -> LSI Corporation
Part Name
Description
Manufacturer
DSP1627 Datasheet PDF : 154 Pages
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DSP1627 Digital Signal Processor
Data Sheet
March 2000
Table of Contents
Contents
Page
1 Features.............................................................. 1
2 Description .......................................................... 1
3 Pin Information.................................................... 3
4 Hardware Architecture ........................................ 7
4.1 DSP1627 Architectural Overview ............. 7
4.2 DSP1600 Core Architectural Overview .. 10
4.3 Interrupts and Trap ................................. 11
4.4 Memory Maps and Wait-States .............. 16
4.5 External Memory Interface (EMI)............ 18
4.6 Bit Manipulation Unit (BMU) ................... 19
4.7 Serial I/O Units (SIOs) ............................ 19
4.8 Parallel Host Interface (PHIF)................. 22
4.9 Bit Input/Output Unit (BIO)...................... 23
4.10 Timer ...................................................... 23
4.11 JTAG Test Port....................................... 24
4.12 Clock Synthesis ...................................... 26
4.13 Power Management ............................... 29
5 Software Architecture ....................................... 36
5.1 Instruction Set......................................... 36
5.2 Register Settings .................................... 45
5.3 Instruction Set Formats .......................... 55
6 Signal Descriptions ........................................... 61
6.1 System Interface..................................... 61
6.2 External Memory Interface ..................... 63
6.3 Serial Interface #1 .................................. 64
6.4 Parallel Host Interface or Serial
Interface #2 and Control I/O Interface .... 65
6.5 Control I/O Interface ............................... 65
6.6 JTAG Test Interface ............................... 66
7 Mask-Programmable Options ........................... 67
7.1 Input Clock Options ................................ 67
7.2 Memory Map Options ............................. 67
7.3 ROM Security Options............................ 67
8 Device Characteristics ...................................... 68
8.1 Absolute Maximum Ratings.................... 68
8.2 Handling Precautions ............................. 68
8.3 Recommended Operating Conditions .... 68
8.4 Package Thermal Considerations .......... 69
9 Electrical Characteristics and Requirements .... 70
9.1 Power Dissipation................................... 73
10 Timing Characteristics for 5 V Operation .......... 75
10.1 DSP Clock Generation ........................... 76
10.2 Reset Circuit ........................................... 77
10.3 Reset Synchronization............................ 78
Contents
Page
10.4 JTAG I/O Specifications.......................... 79
10.5 Interrupt .................................................. 80
10.6 Bit Input/Output (BIO) ............................. 81
10.7 External Memory Interface...................... 82
10.8 PHIF Specifications ................................ 86
10.9 Serial I/O Specifications.......................... 92
10.10 Multiprocessor Communication .............. 97
11 Timing Characteristics for 3.0 V Operation ....... 98
11.1 DSP Clock Generation............................ 99
11.2 Reset Circuit ......................................... 100
11.3 Reset Synchronization.......................... 101
11.4 JTAG I/O Specifications........................ 102
11.5 Interrupt ................................................ 103
11.6 Bit Input/Output (BIO) ........................... 104
11.7 External Memory Interface.................... 105
11.8 PHIF Specifications .............................. 109
11.9 Serial I/O Specifications........................ 115
11.10 Multiprocessor Communication ............ 120
12 Timing Characteristics for 2.7 V Operation ..... 121
12.1 DSP Clock Generation.......................... 122
12.2 Reset Circuit ......................................... 123
12.3 Reset Synchronization.......................... 124
12.4 JTAG I/O Specifications........................ 125
12.5 Interrupt ................................................ 126
12.6 Bit Input/Output (BIO) ........................... 127
12.7 External Memory Interface.................... 128
12.8 PHIF Specifications .............................. 132
12.9 Serial I/O Specifications........................ 138
12.10 Multiprocessor Communication ............ 143
13 Crystal Electrical Characteristics and
Requirements.................................................. 144
13.1 External Components for the Crystal
Oscillator............................................... 144
13.2 Power Dissipation ................................. 144
13.3 LC Network Design for Third
Overtone Crystal Circuits...................... 147
13.4 Frequency Accuracy Considerations .... 149
14 Outline Diagrams ............................................ 152
14.1 100-Pin BQFP (Bumpered Quad
Flat Pack).............................................. 152
14.2 100-Pin TQFP (Thin Quad Flat Pack)... 153
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