DSP1620 View Datasheet(PDF) - Agere -> LSI Corporation
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DSP1620 Datasheet PDF : 114 Pages
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DSP1628 Digital Signal Processor
Preliminary Data Sheet
February 1997
10 Timing Characteristics for 2.7 V Operation (continued)
VIH
PCSN VIL
VIH
PDS VIL
VIH
PRWN VIL
VIH
PBSEL VIL
VIH
PSTAT VIL
PB [7:0]
16-bit READ
t41
t43
t45
t49
t42
t44
t46
t50
t154
16-bit WRITE
t43
t44
t47
t48
t51
t52
Figure 24. PHIF Motorola Mode Signaling (Read and Write) Timing Diagram
5-4038 (C).a
Table 88. Timing Requirements for PHIF Motorola Mode Signaling
Abbreviated Reference
t41
t42
t43
t44
t45*
t46*
t47*
t48*
t51*
t52*
Parameter
PDS† to PCSN Setup (valid to low)
PCSN to PDS† Hold (high to invalid)
PRWN to PCSN Setup (valid to low)
PCSN to PRWN Hold (high to invalid)
PSTAT to PCSN Setup (valid to low)
PCSN to PSTAT Hold (high to invalid)
PBSEL to PCSN Setup (valid to low)
PCSN to PBSEL Hold (high to invalid)
PB Write to PCSN Setup (valid to high)
PCSN to PB Write Hold (high to invalid)
Min
Max
Unit
0
—
ns
0
—
ns
4
—
ns
0
—
ns
4
—
ns
0
—
ns
6
—
ns
0
—
ns
10
—
ns
4
—
ns
Table 89. Timing Characteristics for PHIF Motorola Mode Signaling
Abbreviated Reference
Parameter
Min
t49*
PCSN to PB Read (low to valid)
—
t50*
PCSN to PB Read Hold (high to invalid)
0
t154
PCSN to PB Read 3-state (high to 3-state)
—
Max
12
—
8
Unit
ns
ns
ns
* This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can also
be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. For
example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low after
PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to PCSN
should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.
† PDS is programmable to be active-high or active-low. It is shown active-low in Figures 24 and 25. POBE and PIBF may be programmed to be
the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
99
Lucent Technologies Inc.
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