DSP1620 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

DSP1620

DSP1627 Digital Signal Processor

Agere -> LSI Corporation 

DSP1628 Digital Signal Processor

Preliminary Data Sheet

February 1997

4 Hardware Architecture (continued)

The AWAIT bit should be set from within the cache if the

code which is executing resides in external ROM where

more than one wait-state has been programmed. This

ensures that an interrupt will not disturb the device from

completely entering the sleep state.

For additional power savings, set ioc = 0x0180 and tim-

erc = 0x0040 in addition to setting alf = 0x8000. This

will hold the CKO pin low and shut down the timer and

prescaler (see Table 42 and Table 35).

For a description of the control mechanisms for putting

the DSP into low-power modes, see Section 4.13, Pow-

er Management.

4.4 Memory Maps and Wait-States

The DSP1600 core implements a modified Harvard ar-

chitecture that has separate on-chip 16-bit address and

data buses for the instruction/coefficient (X) and data

(Y) memory spaces. Table 5 shows the instruction/coef-

ficient memory space maps for both the DSP1628x16

and DSP1628x08.

The DSP1628 provides a multiplexed external bus

which accesses external RAM (ERAM) and ROM (ER-

OM). Programmable wait-states are provided for exter-

nal memory accesses. The instruction/coefficient

memory map is configurable to provide application flex-

ibility. Table 6 shows the data memory space, which

has one map.

Instruction/Coefficient Memory Map Selection

In determining which memory map to use, the proces-

sor evaluates the state of two parameters. The first is

the LOWPR bit (bit 14) of the alf register. The LOWPR

bit of the alf register is initialized to 0 automatically at re-

set. LOWPR controls the starting address in memory

assigned to 1K banks of dual-port RAM. If LOWPR is

low, internal dual-port RAM begins at address 0xC000.

If LOWPR is high, internal dual-port RAM begins at ad-

dress 0x0. LOWPR also moves IROM from 0x0 in

MAP1 to 0x4000 in MAP3, and EROM from 0x0 in

MAP2 to 0x4000 in MAP4.

The second parameter is the value at reset of the EXM

pin (pin 27 or pin 14, depending upon the package

type). EXM determines whether the internal 48 Kwords

ROM (IROM) will be addressable in the memory map.

The Lucent Technologies development system tools,

together with the on-chip HDS circuitry and the JTAG

port, can independently set the memory map. Specifi-

cally, during an HDS trap, the memory map is forced to

MAP1. The user's map selection is restored when the

trap service routine has completed execution.

MAP1

MAP1 has the IROM starting at 0x0 and 1 Kword banks

of DPRAM starting at 0xC000. MAP1 is used if

DSP1628 has EXM low at reset and the LOWPR pa-

rameter is programmed to zero. It is also used during an

HDS trap.

MAP2

MAP2 differs from MAP1 in that the lowest 48 Kwords

reference external ROM (EROM). MAP2 is used if EXM

is high at reset, the LOWPR parameter is programmed

to zero, and an HDS trap is not in progress.

MAP3

MAP3 has the 1 Kword banks of DPRAM starting at

address 0x0. In MAP3, the 48 Kwords of IROM start at

0x4000. MAP3 is used if EXM is low at reset, the

LOWPR bit is programmed to 1, and an HDS trap is not

in progress. Note that this map is not available if the

secure mask-programmable option has been ordered.

MAP4

MAP4 differs from MAP3 in that addresses above

0x4000 reference external ROM (EROM). This map is

used if the LOWPR bit is programmed to 1, an HDS trap

is not in progress, and, either EXM is high during reset,

or the secure mask-programmable option has been or-

dered.

Whenever the chip is reset using the RSTB pin, the de-

fault memory map will be MAP1 or MAP2, depending

upon the state of the EXM pin at reset. A reset through

the HDS will not reinitialize the alf register, so the previ-

ous memory map is retained.

Boot from External ROM

After RSTB goes from low to high, the DSP1628 comes

out of reset and fetches an instruction from address

zero of the instruction/coefficient space. The physical

location of address zero is determined by the memory

map in effect. If EXM is high at the rising edge of RSTB,

MAP2 is selected. MAP2 has EROM at location zero;

thus, program execution begins from external memory.

If EXM is high and INT1 is low when RSTB rises, the

mwait register defaults to 15 wait-states for all external

memory segments. If INT1 is high, the mwait register

defaults to 0 wait-states.

18

Lucent Technologies Inc.

Share Link: