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LC665304A View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
Manufacturer
LC665304A Datasheet PDF : 26 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC665304A, 665306A, 665308A, 665312A, 665316A
Continued from preceding page.
Pin
I/O
Overview
OSC1
OSC2
I System clock oscillator connections
When an external clock is used, leave
O OSC2 open and connect the clock signal
to OSC1.
Output driver type
Options
Ceramic oscillator
or external clock
selection
State after a Standby mode
reset
operation
Selected as
an option
Hold mode:
Oscillator
stopped
Halt mode:
Oscillator
operates
RES
System reset input
I
When the P33/HOLD pin is at the high
level, a low level input to the RES pin will
initialize the CPU.
TEST
CPU test pin
I This pin must be connected to VSS
during normal operation.
VDD
VSS
Power supply pins
Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD.
CMOS output: Complementary output.
OD output: Open-drain output.
User Options
1. Port 0, 1, 4, 5, and 8 output level at reset option
The output levels at reset for I/O ports 0, 1, 4, 5, and 8, in independent 4-bit groups, can be selected from the
following two options.
Option
1. Output high at reset
2. Output low at reset
Conditions and notes
The four bits of ports 0, 1, 4, 5, or 8 are set in a group
The four bits of ports 0, 1, 4, 5, or 8 are set in a group
2. Oscillator circuit options
Main clock
Option
Circuit
Conditions and notes
1. External clock
OSC1
The input has Schmitt characteristics
2. Ceramic oscillator
C1 OSC1
Ceramic oscillator
C2
OSC2
Note: There is no RC oscillator option.
Sub-clock
Option
1. Ports PE0 and PE1
Circuit
DSB
2 Sub-oscillator
(crystal oscillator)
C1
XT1
Crystal oscillator
C2
XT2
Input data
Conditions and notes
No. 5485-7/26

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