CXL5504M View Datasheet(PDF) - Sony Semiconductor

Part Name

Description

Manufacturer

CXL5504M

CMOS-CCD 1H Delay Line for NTSC

Sony Semiconductor 

CXL5504M/P

CMOS-CCD 1H Delay Line for NTSC

For the availability of this product, please contact the sales office.

Description

The CXL5504M/P are CMOS-CCD delay line ICs

that provide 1H delay time for NTSC signals including

the external low-pass filter.

CXL5504M

8 pin SOP (Plastic)

CXL5504P

8 pin DIP (Plastic)

Features

• Single power supply (5V)

• Low power consumption 90mW (Typ.)

• Built-in peripheral circuits

• Clamp level of I/O signal can be selected

Functions

• 905-bit CCD register

• Clock driver

• Autobias circuit

• Input clamp circuit

• Sample and hold circuit

Structure

CMOS-CCD

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage

VDD

6

V

• Operating temperature Topr –10 to +60 °C

• Storage temperature Tstg –55 to +150 °C

• Allowable power dissipation

PD

CXL5504M 350 mW

CXL5504P 480 mW

Recommended Operating Condition (Ta = 25°C)

Supply voltage

VDD

5 ± 5% V

Recommended Clock Conditions (Ta = 25°C)

• Input clock amplitude VCLK 0.4 to 1.0 Vp-p

(0.5Vp-p typ.)

• Clock frequency

fCLK 14.318182 MHz

• Input clock waveform Sine wave

Blook Diagram and Pin Configration (Top View)

Input Signal Amplitude

VSIG 500mVp-p (Typ.), 572mVp-p (Max.)

(at internal clamp condition)

8

7

6

5

Autobias circuit

Bias circuit

CCD

(905bit)

Clamp circuit

1

Output circuit

(S/H 1bit)

I/O control

2

3

Timing circuit

Clock driver

Bias circuit (A)

Bias circuit (B)

4

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–

E89931C79-PS

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