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CXD2434ATQ View Datasheet(PDF) - Sony Semiconductor

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CXD2434ATQ Datasheet PDF : 26 Pages
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CXD2434ATQ
Description of Functions
1. Progressive Scan CCD drive pulse generation
Combining this IC with a crystal oscillator generates a fundamental frequency of 24.5454 MHz.
CCD drive pulse generation is synchronized with the HD and VD inputs.
Set fCL to 780 fHD and fHD to 525 fVD.
The various operations are performed by the TRIG, EFS and ESG inputs. (See the following items.)
<Detection timing for VD, TRIG, EFS and ESG>
CL
1
HD
H1
35
T1
Detection timing for VD,
TRIG, EFS and ESG
After HD input is detected, the status of VD, TRIG, ESG and EFS is detected during T1.
Do not change the status of VD, TRIG, ESG and EFS during T1.
When input is from a non-synchronized system, the low level period for each pulse should be set to 63.5 µs
or longer to prevent misoperation.
2. Reset
The internal register values are undetermined immediately after power-on, so perform one of the following
reset operations.
1. Reset by the RESET pin
Reset is performed by setting the RESET pin low for a period of 80 ns or more. Reset can also be
performed by setting the RESET pin low during power-on and then switching the RESET pin from low to
high when VDD rises to 4.75 V or higher. Note that when reset is performed by the RESET pin, the
electronic shutter settings made by serial input are also reset.
2. Reset by turning off the electronic shutter
Reset is performed by setting the shutter mode to electronic shutter off and inputting VD. Note that in
this case the TRIG, ESG and EFS pins should all be set high.
—8—

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