EL7512 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
EL7512 Datasheet PDF : 8 Pages
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EL7512
The output diode has average current of IO, and peak current
the same as the inductor's peak current. Schottky diode is
recommended and it should be able to handle those currents.
Output voltage ripple is the product of peak inductor current
times the ESR of output capacitor. Low ESR capacitor is to be
used to reduce the output ripple. The minimum output
capacitance of 330µF, 47µF, and 33µF is recommended for
5V, 12V, and 16V for 600kHz switching frequency,
respectively. For 1MHz switching frequency, 220µF, 33µF, and
22µF capacitor can be used for the output voltages. In addition
to the voltage rating, the output capacitor should also be able
to handle the rms current is given by:
ICORMS =
1
–
D
D
+
---------I--L---2-----
ILAVG2
1--1--2--
ILAVG
Output Voltage
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. The current
drawn by the resistor network should be limited to maintain the
overall converter efficiency. The maximum value of the resistor
network is limited by the feedback input bias current and the
potential for noise being coupled into the feedback pin. A
resistor network less than 300k is recommended. The boost
converter output voltage is determined by the relationship:
VOUT
=
VFB
1
+
R-R----21-
where VFB slightly changes with VDD. The curve is shown in
this data sheet.
RC Filter
The maximum voltage rating for the VDD pin is 12V and is
recommended to be about 10V for maximum efficiency to drive
the internal MOSFET. The series resistor R4 in the RC filter
connected to VDD can be utilized to reduce the voltage. If VO is
larger than 10V, then:
R4
=
V-----O-----–-----1---0--
IDD
where IDD is shown in IDD vs FS curve. Otherwise, R4 can be
10 to 51 with C4 = 0.1µF.
Thermal Performance
The EL7512 uses a fused-lead package, which has a reduced
JA of 100°C/W on a four-layer board and 115°C/W on a two-
layer board. Maximizing copper around the ground pins will
improve the thermal performance.
This chip also has internal thermal shut-down set at around
135°C to protect the component.
Layout Considerations
The layout is very important for the converter to function
properly. Power Ground ( ) and Signal Ground (- --)
should be separated to ensure that the high pulse current in
the Power Ground never interferes with the sensitive signals
connected to Signal Ground. They should only be connected at
one point.
The trace connected to pin 8 (FB) is the most sensitive trace. It
needs to be as short as possible and in a “quiet” place,
preferably between PGND or SGND traces.
In addition, the bypass capacitor connected to the VDD pin
needs to be as close to the pin as possible.
The heat of the chip is mainly dissipated through the SGND
pin. Maximizing the copper area around it is preferable. In
addition, a solid ground plane is always helpful for the EMI
performance.
The demo board is a good example of layout based on these
principles. Please refer to the EL7512 Application Brief for the
layout.
FN7290 Rev 1.00
May 23, 2005
Page 7 of 8
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