MC7410VU400LE View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MC7410VU400LE

MPC7410 RISC Microprocessor Hardware Specifications

Unspecified 

Electrical and Thermal Characteristics

Table 1. Absolute Maximum Ratings 1 (continued)

Characteristic

Symbol

Maximum Value

Unit Notes

Rework temperature

Trwk

260

°C

—

Notes:

1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only,

and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device

reliability or cause permanent damage to the device.

2. Caution: Vin must not exceed OVDD or L2OVDD by more than 0.2 V at any time including during power-on reset.

3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 2.0 V at any time including during

power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down

sequences.

4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4 V at any time including during

power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down

sequences.

5. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

6. Mxx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OVDD and have a maximum

value OVDD of –0.3 to 2.8 V.

Figure 2 shows the allowable undershoot and overshoot voltage for the MPC7410.

(L2)OVDD + 20%

(L2)OVDD + 5%

(L2)OVDD

VIH

VIL

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

of tSYSCLK (OVDD)

or tL2CLK (L2OVDD)

Figure 2. Overshoot/Undershoot Voltage

The MPC7410 provides several I/O voltages to support both compatibility with existing systems and migration to

future systems. The MPC7410 core voltage must always be provided at nominal voltage (see Table 3 for actual

recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are provided through separate sets

of supply pins and may be provided at the voltages shown in Table 2. Voltage must be provided to the L2OVDD

power pins even if the interface is not used. The input voltage threshold for each bus is selected by sampling the

state of the voltage select pins BVSEL and L2VSEL at the negation of the signal HRESET. These signals must

remain stable during part operation and cannot change. The output voltage will swing from GND to the maximum

voltage applied to the OVDD or L2OVDD power pins.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

8

Freescale Semiconductor

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