ST72321M6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72321M6

80-pin 8-bit MCU with 32 to 60 Kbytes Flash, ADC, five timers, SPI, SCI, I2C interface

STMicroelectronics 

ST72321M6 ST72321M9

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for

securing the application in critical situations (for

example in case of a power brown-out), and re-

ducing the number of external components. An

overview is shown in Figure 10.

For more details, refer to dedicated parametric

section.

Main features

■ Optional PLL for multiplying the frequency by 2

(not to be used with internal RC oscillator)

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

– 5 Crystal/Ceramic resonator oscillators

– 1 Internal RC oscillator

■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD)

– Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supply or

the EVD pin

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the

range 2 to 4 MHz, the PLL can be used to multiply

the frequency by two to obtain an fOSC2 of 4 to 8

MHz. The PLL is enabled by option byte. If the PLL

is disabled, then fOSC2 = fOSC/2.

Caution: The PLL is not recommended for appli-

cations where timing accuracy is required. See

“PLL Characteristics” on page 146.

Figure 9. PLL Block Diagram

PLL x 2

fOSC

/2

0

fOSC2

1

PLL OPTION BIT

Figure 10. Clock, Reset and Supply Block Diagram

OSC2

OSC1

RESET

VSS

VDD

EVD

MULTI-

OSCILLATOR

(MO)

fOSC

PLL

(option)

RESET SEQUENCE

MANAGER

(RSM)

fOSC2

MAIN CLOCK

CONTROLLER

fCPU

WITH REALTIME

CLOCK (MCC/RTC)

SYSTEM INTEGRITY MANAGEMENT

AVD Interrupt Request

SICSR

AVD AVD AVD LVD

S IE F RF

0

0

0

WDG

RF

WATCHDOG

TIMER (WDG)

LOW VOLTAGE

DETECTOR

(LVD)

0

AUXILIARY VOLTAGE

DETECTOR

1

(AVD)

23/175

Share Link: