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SM565 View Datasheet(PDF) - Sharp Electronics

Part Name
Description
Manufacturer
SM565
Sharp
Sharp Electronics Sharp
SM565 Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
4-Bit Single-Chip Microcomputer
SM565
Timer/Counter and the SND Signal
The timer/counter consists of an 8-bit count register
(TC) and an 8-bit modulo register (TM).
The count register is an 8-bit incremental binary
counter. It is incremented by one at the falling edge of
its count pulse (CP) input. If the count register over-
flows, the timer interrupt request flag IFT is set, and the
contents of the modulo register (TM) are loaded into
the count register (see Figure 7).
The count pulse Cp can be selected from divider sig-
nals fIn and f0, and the system clock, by using the mode
register RD. If the count register (TC) overflows, the
SND flag reverses its status at the falling edge of the
TC. A sound signal can be obtained at the TC output by
putting P2 in output mode and sending a ‘1’ to pin P23
(see Figure 8).
Serial Interface and IFS
The serial interface consists of an 8-bit shift register
(SB) and a 3-bit counter, which is used to input and out-
put the serial data. The serial clock can be selected
with either an internal clock (system clock) or an exter-
nal clock.
In serial shift operations, the highest bit data of the
shift register (SB) is output from the SO pin, and the data
input from the SI pin at the rising edge of a serial clock is
loaded into the lowest bit of the shift register. When the
internal clock is used, immediately after the SIO instruc-
tion is executed, the serial operation begins and stops
with eight clocks which are output from the SCK pin.
Upon completion of an 8-bit shift operation, the
serial I/O ending flag IFS is set each time a 3-bit
counter overflows, and an interrupt request occurs.
LDTC
B, A
STTM
TM (8)
OVERFLOW
STTC
COUNT PULSE
CP
TC (8)
BINARY COUNTER
INT T + TSTT
IFT
SQ
R
565-9
Figure 7. Timer/Counter
TC(8)
SND FLAG
TQ
R23
A
RF3
Figure 8. SND Signal
P23
565-10
P32/SO
P30/SI
P31/SCK
8 - BIT SB REGISTER
SERIAL CLOCK OUTPUT
DATA SHIFT REQUEST
SERIAL
CLOCK
SELECTOR
3 BIT CNT
TRANSFER END SIGNAL
SQ
REGISTER
INTERNAL CLOCK
EXTERNAL CLOCK
φ1
QR
S
TSTS
R
SIO
IFS FLAG
Figure 9. Serial Interface
565-11
Microcomputer Data Sheet
11

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