SM565 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
Manufacturer
SM565 Datasheet PDF : 20 Pages
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SM565
4-Bit Single-Chip Microcomputer
SYSTEM CONFIGURATION
ROM and Program Counter
The on-chip ROM has a configuration of 128-page ×
64-step × 8-bit, and stores programs and table data.
The program counter consists of a 7-bit page
address counter PU and a 6-bit binary counter PL used
to specify the steps within a page.
The locations shown in Figure 3 are allocated in the
on-chip ROM.
Stack Pointer (SP)
The stack pointer (SP) is an 8-bit shift register which
holds the starting address of the stack area of RAM
space. Immediately after the reset, the contents of the
stack pointer are uninitialized and must be set to an
appropriate value. If, for instance, the initial value of the
stack pointer is set to 80H, the data memory is begin-
ning with the highest address (excluding the display
RAM area). 7FH is usable as a stack area.
RAM
Data memory has a 256-word × 4-bit configuration,
and is used to store processing data and other informa-
tion. Data memory is also used as a stack area to save
register values, the program counter value and pro-
gram status word (PSW) at the time a subroutine jump
or an interrupt occurs. Figure 4 shows the RAM config-
uration. 64 × 4-bit of entire RAM space is used as a dis-
play RAM area from which data is output to LCD
segment driving pins. A LCD with a 1/4 duty and 1/3
bias format can be directly driven by writing display
data into the display RAM area. The display RAM out-
puts are, as shown in Figure 5, connected to segment
output pins S0 to S63 for individual set of common out-
puts H1 to H4. The segment output pins provide a sin-
gle digit of display RAM data M0 to M3, as a LCD driving
waveform signal according to H1 to H4 outputs. The
operations of the display RAM are identical to those of
other RAM areas.
PAGE 0, ADDRESS 0
PAGE 1, ADDRESS 0
ADDRESS 2
ADDRESS 4
ADDRESS 6
ADDRESS 8
RESET
INTT
INTA
INTS
INTB
INTV
Program execution starts with this address
at power on or RESET
First address of the timer/counter interrupt
service routine
First address of the interrupt routine that services
the dividers of signal interrupt
First address of the interrupt routine that services
the serial I/O interrupt
First address of the interrupt routine that services
the PO input signal
First address of the divider overflow interrupt routine
..
.
PAGE 10H, ADD. RESS 0
.
.
..
.
ADDRESS 3EH
..
.
.. Jump address for TRS subroutine instruction
. (PU = 10H, PL0 = 0, PL5 = 0)
...
...
PAGE 7FH, ADDRESS 3FH
Last ROM address
565-5
Figure 3. Program ROM Map
8
Microcomputer Data Sheet
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