MC10H351(2000) View Datasheet(PDF) - ON Semiconductor
Part Name
Description
Manufacturer
MC10H351 Datasheet PDF : 4 Pages
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MC10H351
Quad TTL/NMOS to PECL*
Translator
The MC10H351 is a quad translator for interfacing data between a
saturated logic section and the PECL section of digital systems when
only a +5.0 Vdc power supply is available. The MC10H351 has
TTL/NMOS compatible inputs and PECL complementary
open–emitter outputs that allow use as an inverting/non–inverting
translator or as a differential line driver. When the common strobe
input is at a low logic level, it forces all true outputs to the PECL low
logic state (≈ +3.2 V) and all inverting outputs to the PECL high logic
state (≈ +4.1 V).
The MC10H351 can also be used with the MC10H350 to transmit
and receive TTL/NMOS information differentially via balanced
twisted pair lines.
• Single +5.0 Power Supply
• All VCC Pins Isolated On Chip
• Differentially Drive Balanced Lines
• tpd = 1.3 nsec Typical
LOGIC DIAGRAM
B IN 7
A IN 8
D IN 12
C IN 14
COMMON 9
STROBE
1 B OUT
2 B OUT
5 A OUT
4 A OUT
16 D OUT
17 D OUT
19 C OUT
18 C OUT
VCC (+5.0 VDC) = PINS 6, 11, 15, 20
GND = PIN 10
DIP PIN ASSIGNMENT
B OUT
1
B OUT
2
20
ECL VCC
19
C OUT
N.C.
3
18
C OUT
A OUT
4
17
D OUT
A OUT
5
16
D OUT
VCC
6
B IN
7
15
VCC 2
14
C IN
A IN
8
13
N.C.
COMMON
STROBE
9
12
D IN
GND
10
11
TTL VCC
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP–20
L SUFFIX
CASE 732
MARKING
DIAGRAMS
20
MC10H351L
AWLYYWW
1
PDIP–20
P SUFFIX
CASE 738
20
MC10H351P
AWLYYWW
1
1
PLCC–20
FN SUFFIX
CASE 775
10H351
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10H351L
CDIP–20
18 Units/Rail
MC10H351P
PDIP–20
18 Units/Rail
MC10H351FN PLCC–20
46 Units/Rail
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 6
Publication Order Number:
MC10H351/D
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